Showing papers on "Subthreshold conduction published in 2020"

Is negative capacitance FET a steep-slope logic switch?

Abstract: The negative-capacitance field-effect transistor(NC-FET) has attracted tremendous research efforts. However, the lack of a clear physical picture and design rule for this device has led to numerous invalid fabrications. In this work, we address this issue based on an unexpectedly concise and insightful analytical formulation of the minimum hysteresis-free subthreshold swing (SS), together with several important conclusions. Firstly, well-designed MOSFETs that have low trap density, low doping in the channel, and excellent electrostatic integrity, receive very limited benefit from NC in terms of achieving subthermionic SS. Secondly, quantum-capacitance is the limiting factor for NC-FETs to achieve hysteresis-free subthermionic SS, and FETs that can operate in the quantum-capacitance limit are desired platforms for NC-FET construction. Finally, a practical role of NC in FETs is to save the subthreshold and overdrive voltage losses. Our analysis and findings are intended to steer the NC-FET research in the right direction.

Stochastic resonance in MoS2 photodetector.

Abstract: In this article, we adopt a radical approach for next generation ultra-low-power sensor design by embracing the evolutionary success of animals with extraordinary sensory information processing capabilities that allow them to survive in extreme and resource constrained environments. Stochastic resonance (SR) is one of those astounding phenomena, where noise, which is considered detrimental for electronic circuits and communication systems, plays a constructive role in the detection of weak signals. Here, we show SR in a photodetector based on monolayer MoS2 for detecting ultra-low-intensity subthreshold optical signals from a distant light emitting diode (LED). We demonstrate that weak periodic LED signals, which are otherwise undetectable, can be detected by a MoS2 photodetector in the presence of a finite and optimum amount of white Gaussian noise at a frugal energy expenditure of few tens of nano-Joules. The concept of SR is generic in nature and can be extended beyond photodetector to any other sensors. Here, the authors take advantage of stochastic resonance in a photodetector based on monolayer MoS2 for measuring otherwise undetectable, ultra-low-intensity, subthreshold optical signals from a distant light emitting diode in the presence of a finite and optimum amount of white Gaussian noise.

A review on performance comparison of advanced MOSFET structures below 45 nm technology node

Abstract: CMOS technology is one of the most frequently used technologies in the semiconductor industry as it can be successfully integrated with ICs. Every two years the number of MOS transistors doubles because the size of the MOSFET is reduced. Reducing the size of the MOSFET reduces the size of the channel length which causes short channel effects and it increases the leakage current. To reduce the short channel effects new designs and technologies are implemented. Double gate MOSFET design has shown improvement in performance as amplifiers over a single MOSFET. Silicon-based MOSFET design can be used in a harsh environment. It has been used in various applications such as in detecting biomolecules. The increase in number of gates increases the current drive capability of transistors. GAA MOSFET is an example of a quadruple gate around the four sides of channel that increases gate control over the channel region. It also increases effective channel width that improves drain current and reduces leakage current keeping short channel effects under limit. Junctionless MOSFET operates faster and uses less power with increase in ON-state current leading to a good value of ION/IOFF ratio. In this paper, several gate and channel engineered MOSFET structures are analyzed and compared for sub 45 nm technology node. A comparison among different MOSFET structures has been made for subthreshold performance parameters in terms of IOFF, subthreshold slope and DIBL values. The analog/RF performance is analyzed for transconductance, effective transistor capacitances, stability factor and critical frequency. The paper also covers different applications of advance MOSFET structures in analog/digital or IoT/ biomedical applications.

WSe2/SnSe2 vdW heterojunction Tunnel FET with subthermionic characteristic and MOSFET co-integrated on same WSe2 flake

Abstract: Two-dimensional/two-dimensional (2D/2D) heterojunctions form one of the most versatile technological solutions for building tunneling field effect transistors because of the sharp and potentially clean interfaces resulting from van der Waals assembly. Several evidences of room temperature band-to-band tunneling (BTBT) have been recently reported, but only few tunneling devices have been proven to break the Boltzmann limit of the minimum subthreshold slope, 60 mV per decade at 300 K. Here, we report the fabrication and characterization of a vertical p-type Tunnel FET (TFET) co-integrated on the same flake with a p-type MOSFET in a WSe2/SnSe2 material system platform. Due to the selected beneficial band alignment and to a van der Waals device architecture having an excellent heterostructure 2D–2D interface, the reported tunneling devices have a sub-thermionic point swing, reaching a value of 35 mV per decade, while maintaining excellent ON/OFF current ratio in excess of 105 at VDS = 500 mV. The TFET characteristics are directly compared with the ones of a WSe2 MOSFET realized on the very same flake used in the heterojunction. The tunneling device clearly outperforms the 2D MOSFET in the subthreshold region, crossing its characteristic over several orders of magnitude of the output current and providing better digital and analog figures of merit.

A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks

Abstract: This paper presents a strong silicon physical unclonable function (PUF) resistant to machine learning (ML) attacks. The PUF, termed the subthreshold current array PUF (SCA-PUF), consists of a pair of two-dimensional transistor arrays and a low-offset comparator. The proposed 65-bit SCA-PUF is fabricated in a 130nm process and allows 265 challenge-response pairs (CRPs). It consumes 68nW and 11pJ/bit while exhibiting high uniqueness, uniformity, and randomness. It achieves bit error rate (BER) of 5.8% for the temperature range of −20 to 80°C and supply voltage variation of ±10%. The calibration-based CRP selection method improves BER to 0.4% with a 42% loss of CRPs. When subjected to ML attacks, the prediction error stays over 40% on 104 training points, which shows negligible loss in PUF unpredictability and $\sim 100\times $ higher resilience than the 65-bit arbiter PUF, 3-XOR PUF, and 3-XOR lightweight (LW) PUF.

Atomic threshold-switching enabled MoS2 transistors towards ultralow-power electronics.

Abstract: Power dissipation is a fundamental issue for future chip-based electronics. As promising channel materials, two-dimensional semiconductors show excellent capabilities of scaling dimensions and reducing off-state currents. However, field-effect transistors based on two-dimensional materials are still confronted with the fundamental thermionic limitation of the subthreshold swing of 60 mV decade−1 at room temperature. Here, we present an atomic threshold-switching field-effect transistor constructed by integrating a metal filamentary threshold switch with a two-dimensional MoS2 channel, and obtain abrupt steepness in the turn-on characteristics and 4.5 mV decade−1 subthreshold swing (over five decades). This is achieved by using the negative differential resistance effect from the threshold switch to induce an internal voltage amplification across the MoS2 channel. Notably, in such devices, the simultaneous achievement of efficient electrostatics, very small sub-thermionic subthreshold swings, and ultralow leakage currents, would be highly desirable for next-generation energy-efficient integrated circuits and ultralow-power applications. Here, the authors demonstrate an atomic threshold-switching field-effect transistor constructed by integrating a metal filamentary switch with a two-dimensional MoS2 channel, and obtain abrupt steepness in the turn-on characteristics and 4.5 mV/dec subthreshold swing over five decades.

Ambipolar Deep-Subthreshold Printed-Carbon-Nanotube Transistors for Ultralow-Voltage and Ultralow-Power Electronics.

Abstract: The development of ultralow-power and easy-to-fabricate electronics with potential for large-scale circuit integration (i.e., complementary or complementary-like) is an outstanding challenge for emerging off-the-grid applications, e.g., remote sensing, "place-and-forget", and the Internet of Things. Herein we address this challenge through the development of ambipolar transistors relying on solution-processed polymer-sorted semiconducting carbon nanotube networks (sc-SWCNTNs) operating in the deep-subthreshold regime. Application of self-assembled monolayers at the active channel interface enables the fine-tuning of sc-SWCNTN transistors toward well-balanced ambipolar deep-subthreshold characteristics. The significance of these features is assessed by exploring the applicability of such transistors to complementary-like integrated circuits, with respect to which the impact of the subthreshold slope and flatband voltage on voltage and power requirements is studied experimentally and theoretically. As demonstrated with inverter and NAND gates, the ambipolar deep-subthreshold sc-SWCNTN approach enables digital circuits with complementary-like operation and characteristics including wide noise margins and ultralow operational voltages (≤0.5 V), while exhibiting record-low power consumption (≤1 pW/μm). Among thin-film transistor technologies with minimal material complexity, our approach achieves the lowest energy and power dissipation figures reported to date, which are compatible with and highly attractive for emerging off-the-grid applications.

A Subthreshold Cross-Coupled Hybrid Charge Pump for 50-mV Cold-Start

Abstract: In this article, a fully-integrated switched-capacitor DC-DC converter based on a Dickson charge pump able to work with input voltage levels that force the transistors working in subthreshold region is presented. The proposed topology exploits resistors in the charge transfer switch in order to overcome the limits of conventional solutions when working in the subthreshold regime. Post-layout simulations using a 28-nm FD-SOI technology show that the CP can boost an input voltage as low as 50 mV to a maximum output voltage of 270 mV, keeping a settling time about 25X lower than the conventional dual-branch cross-coupled charge pump and a voltage conversion efficiency higher than 76%. The proposed topology is particularly suited for the start-up of power management units supplied by thermoelectric generators.

A 0.36-V 5-MS/s Time-Mode Flash ADC With Dickson-Charge-Pump-Based Comparators in 28-nm CMOS

Abstract: Dickson charge-pump (CP) is proposed here to realize a voltage-to-time converter (VTC) within an array of time-domain comparators of a 54-level time-mode subthreshold flash ADC operating at 0.36V. Two identical CPs in each of the 54 ADC slices convert the input and reference voltages into variable-slope ramp signals fed into comparators for ‘flash’ quantization. Considering the fact that the comparator’s evaluation time gets severely degraded at subthreshold input voltages, the proposed ADC delivers the maximum bandwidth by means of the inherent input voltage boosting by the Dickson CPs. The proposed architecture quantizes the analog input signal into time with CPs and then into digital domain with latches and simple logic, without using any analog-intensive circuits such as amplifiers and current sources, thus yielding a digitally friendly implementation. Measurement results show peak ENOB of 5.04-bit, SNDR of 32.1dB at the peak, power consumption of $88~\mu \text{W}$ . The conversion rate of 5 MS/s is the highest among near- and subthreshold ADCs.

A 48 pW, 0.34 V, 0.019%/V Line Sensitivity Self-Biased Subthreshold Voltage Reference With DIBL Effect Compensation

Abstract: This paper presents a self-biased subthreshold CMOS voltage reference for low-power and low-voltage applications. To achieve near-zero line sensitivity and high PSRR, a compensation structure utilizing the drain-induced-barrier-lowering (DIBL) effect is proposed to sink a supply dependent current from the output branch of a self-biased CMOS reference, which cancels the bias current’s dependence on the supply voltage due to the DIBL effect. Fabricated in a 0.18- $\mu \text{m}$ CMOS technology, the measurement results demonstrate that the proposed circuit could operate under a minimum supply voltage of 0.34 V and generate a reference voltage of 147 mV, while consuming only 48 pW power. The PSRRs measured at 1 Hz and 10 kHz are −70.6 dB and −50.2 dB, respectively. For 39 measured samples, the mean line sensitivity is 0.019%/V in a supply voltage range from 0.34 to 1.8 V, and the average temperature coefficients before and after trimming are 64.81 and 10.06 ppm/°C in 0 ~ 100 °C temperature range, respectively. The total area of the voltage reference circuit is 0.0332mm2.

A Journey from Bulk MOSFET to 3 nm and Beyond

Abstract: To overcome scaling issues such as controlling gate leakage, drain induced barrier lowering, higher subthreshold conduction, polysilicon gate depletion, and other short channel effects various engineering proposed. The gate dielectric, metal work function, and device structural engineering enabled the semiconductor industry to make a transition from the conventional planar MOSFET towards a revolutionary 3D tri-gate structure called FinFET. FinFET is one of the fundamental invention in the semiconductor industry, which replaced the planar CMOS technology around 22 nm technology. By following Moore’s law, it accelerated the scaling to 7 nm, but at 5 nm, in the same way, GAAFET replaced FinFET due to technological hurdles. Nanosheet, which is one type of GAAFET are in the recent trend. But researchers are trying to explore the possibilities to continue the miniaturization beyond 3 nm by combining the effect of non-silicon channel material such as Ge, InGaAs, or 2D materials with nanosheet, which will improve the functionality of the device while going down in the technology node. In this survey, an attempt has been made for the structure present till 7 nm process. Also, a few new proposals in research to take the scaling up to 3 nm and beyond are included. The future innovations may put an intercept on the slowing down of Moore’s law, and bring the miniaturization back in the track.

0.3 pJ/Bit Machine Learning Resistant Strong PUF Using Subthreshold Voltage Divider Array

Abstract: This brief presents a subthreshold voltage divider based strong physical unclonable function (PUF). The PUF derives its uniqueness from random mismatch in threshold voltage in an inverter with gate and drain shorted and biased in subthreshold region. The nonlinear current-voltage relationship in subthreshold region also makes the proposed PUF resistant to machine learning (ML) based attacks. Prediction accuracy of PUF response with logistic regression, support vector machine (SVM) and multi-layer perceptron (MLP) is close to 51%. A prototype PUF fabricated in 65nm consumes only 0.3pJ/bit, and achieves the best combination of energy efficiency and resistance to ML attacks. The measured inter and intra hamming distance (HD) for the PUF are 0.5026 and 0.0466 respectively.

0.5 V Fifth-Order Butterworth Low-Pass Filter Using Multiple-Input OTA for ECG Applications

Abstract: This paper presents a 0.5 V fifth-order Butterworth low-pass filter based on multiple-input operational transconductance amplifiers (OTA). The filter is designed for electrocardiogram (ECG) acquisition systems and operates in the subthreshold region with nano-watt power consumption. The used multiple-input technique simplifies the overall structure of the OTA and reduces the number of active elements needed to realize the filter. The filter was designed and simulated in the Cadence environment using a 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) process from Taiwan Semiconductor Manufacturing Company (TSMC). Simulation results show that the filter has a bandwidth of 250 Hz, a power consumption of 34.65 nW, a dynamic range of 63.24 dB, attaining a figure-of-merit of 0.0191 pJ. The corner (process, voltage, temperature: PVT) and Monte Carlo (MC) analyses are included to prove the robustness of the filter.

A Comparative Study on Scaling Capabilities of Si and SiGe Nanoscale Double Gate Tunneling FETs

Abstract: In the last few years, an accelerated trend towards the miniaturization of nanoscale circuits has been recorded. In this context, the Tunneling Field-Effect Transistors (TFETs) are gaining attention because of their good subthreshold characteristics, high scalability and low leakage current. However, they suffer from low values of the ON-state current and severe ambipolar transport mechanism. The aim of this work is to investigate the performance of SiGe nanoscale Double Gate TFET device including low doped drain region. The electrical performance of the considered device is investigated numerically using ATLAS 2D simulator, where both scaling and reliability aspects of the proposed design are reported. In this context, we address the impact of the channel length, traps density and drain doping parameters on the variation of some figures of merit of the device namely the swing factor and the ION/IOFF ratio. The obtained results indicate the superior immunity of the proposed design against traps induced degradation in comparison to the conventional TFET structure. Therefore, this work can offer more insights regarding the benefit of adopting channel materials and drain doping engineering techniques for future reliable low-power nanoscale electronic applications.

A −40 °C to 120 °C, 169 ppm/°C Nano-Ampere CMOS Current Reference

Abstract: This brief presents a nano-ampere CMOS current reference (CCR) for low power application with a wide temperature range from −40°C to 120°C. The current reference is generated by the division of a temperature-independent voltage and resistance in a simple way. The low temperature-independent voltage is generated based on the threshold voltage difference between two same-type NMOS transistors with different channel lengths working in the subthreshold region, while the temperature-independent resistance is made up by two poly resistors, whose temperature coefficients are opposite. By designing a low voltage to allow for a small resistance, the CCR circuit takes a small chip area while generating nano-ampere current. The proposed CCR circuit was implemented in a standard 0.18- ${\mu }\text{m}$ CMOS process and its active area is 0.054 mm2. Among the measured 10 samples, the average output current is 11.6 nA and the average temperature coefficient is 169 ppm/°C.

Design and Analysis of Heavily Doped n+ Pocket Asymmetrical Junction-Less Double Gate MOSFET for Biomedical Applications

Abstract: The Complementary Metal-Oxide Semiconductor (CMOS) technology has evolved to a great extent and is being used for different applications like environmental, biomedical, radiofrequency and switching, etc. Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) based biosensors are used for detecting various enzymes, molecules, pathogens and antigens efficiently with a less time-consuming process involved in comparison to other options. Early-stage detection of disease is easily possible using Field-Effect Transistor (FET) based biosensors. In this paper, a steep subthreshold heavily doped n+ pocket asymmetrical junctionless MOSFET is designed for biomedical applications by introducing a nanogap cavity region at the gate-oxide interface. The nanogap cavity region is introduced in such a manner that it is sensitive to variation in biomolecules present in the cavity region. The analysis is based on dielectric modulation or changes due to variation in the bio-molecules present in the environment or the human body. The analysis of proposed asymmetrical junctionless MOSFET with nanogap cavity region is carried out with different dielectric materials and variations in cavity length and height inside the gate–oxide interface. Further, this device also showed significant variation for changes in different introduced charged particles or region materials, as simulated through a 2D visual Technology Computer-Aided Design (TCAD) device simulator.

Hf 0.5 Zr 0.5 O 2 -Based Ferroelectric Gate HEMTs With Large Threshold Voltage Tuning Range

Abstract: AlGaN/GaN high-electron-mobility transistors (HEMTs) with Hr0.5 Zr0.5O2 ferroelectric gate stacks exhibiting significant ferroelectric switching for threshold voltage control are experimentally demonstrated. Ferroelectric gate HEMTs (FeHEMTs) with large threshold voltage tuning range of 2.8 V were obtained, with an on/off ratio of $\sim {10}^{{{5}}}$ based on a GaN-channel HEMT structure suitable for RF applications. Improved subthreshold performance has also been achieved compared to conventional MIS-HEMTs, with reduction in average sub-threshold swing (SSavg) by a factor of 2. As a consequence of the significant ferroelectric polarization achieved on AlGaN/GaN heterostructures, Hr0.5 Zr0.5O2 based ferroelectric gate AlGaN/GaN HEMTs appear promising for nonvolatile and reconfigurable RF and microwave applications.

Subthreshold biased enhanced bulk-driven double recycling current mirror OTA

Abstract: This paper presents a single-stage bulk-driven double recycling low-voltage low-power operational transconductance amplifier (OTA) operating in subthreshold region. The proposed OTA utilizes double recycling topology and provides enough open loop voltage gain, slew rate, and unity gain frequency (UGF). The flipped voltage follower-based adaptively biased input differential pair working in class AB mode has ensured dynamic current boosting and increased slew rate. Further, the proposed OTA has utilized partial positive feedback to mitigate some of the performance reduction caused by the bulk-driven topology. The simulation results of the proposed OTA have ensured open loop gain of 79.5 dB, UGF of 37.1 kHz, and phase margin of 64°. It operates with dual power supply of ± 0.25 V and consumes low power of 60 nW. These performance parameters validate its usefulness for LV, LP and low-frequency applications. The process, voltage, and temperature variation effects on low-frequency voltage gain, UGF, and phase margin of the proposed OTA has also been investigated with process corner simulations. The proposed OTA is designed and simulated in UMC 180 nm standard n-tub bulk CMOS process technology utilizing Tanner EDA tools.

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Abstract: Cryogenic device models are essential for the reliable design of the cryo-CMOS electronic interface necessary to build future large-scale quantum computers. This paper reports the characterization of the drain-current mismatch of NMOS and PMOS devices fabricated in a commercial 40-nm bulk CMOS process over the temperature range from 4.2K to 300 K. By analysing the variability of device parameters over a wide range of device area and length, the validity of the Pelgrom area-scaling law is assessed for the threshold voltage, the current factor and the subthreshold swing. The Croon model is employed to model the drain-current mismatch in moderate to strong inversion, while the weak inversion region is modeled by taking the subthreshold slope variability into account. This results in the first model capable of predicting CMOS-device mismatch over all operating regions and in the whole temperature range from 300K down to 4.2K.

An Energy Efficient Level Shifter Capable of Logic Conversion From Sub-15 mV to 1.2 V

Abstract: We propose architectural advances in low voltage, energy-efficient, level shifters. A write assist circuit is introduced, to support the up-conversion of deep subthreshold inputs. We also present an approach to reduce the leakage current in split signal output stages. A prototype was created in a 130 nm bulk CMOS process, and some samples were successfully tested for input voltages as low as 5 mV. For 10 measured samples, the mean functional, minimum, input voltage was 31.1 mV. By applying body bias to selected NMOS transistors to compensate for process and mismatch variation, the measured mean minimum input voltage was lowered to 14.3 mV. The leakage reduction in the split control output driver reduces the driver leakage by a factor of 8. The designed level shifter was found to be energy efficient compared to published structures, it consumed an average of 25.9 fJ per conversion in post-layout simulations and the delay was measured to 21.08 ns at 300 mV input signals.

Linearity Performance Analysis Due to Lateral Straggle Variation in Hetero-Stacked TFET

Abstract: In this paper, we examine the impact of variation in the lateral straggle parameter on linearity and reliability performance for the Hetero-stacked TFET. By incorporating hetero-stack in the Source, both the subthreshold as well as the drain current can be improved. Although the tunnel field effect transistor is considered a valid candidate to replace the MOSFET for low power applications, the device performance depends on the precision in the fabrication process. During fabrication process, ion implantation technique is used to realize the variation in the tilt angle. This variation causes an extension of dopants from the regions of source and drain to the channel, which significantly affects the performance of the device. The linearity and reliability performances of the Hetero-stacked TFET (HS-TFET) are analyzed by varying the lateral straggle parameter (σ) from 0 to 8 nm. A higher value of the lateral straggling parameter causes an increase in the on current due to the enhanced electron tunneling rate. However, linearity performance tends to deteriorate as the lateral straggle parameter increases. The linearity and reliability of the device are studied in terms of transconductances of higher order (gm2 and gm3), VIP2, VIP3, IIP3, IMD3 and 1-dB compression point.

Low-Power Efficient p+ Si 0.7 Ge 0.3 Pocket Junctionless SGTFET with Varying Operating Conditions

Abstract: A new low-power Si1−xGex pocket junctionless single-gate tunnel field-effect transistor (JLSGTFET) is designed to achieve steep subthreshold performance and a better ION/IOFF ratio (∼ 108) in sub-20-nanometer technology node. The mole fraction of Ge represented by x is kept at 0.3 for the SiGe pocket region. The proposed JLSGTFET shows better performance with a Ge mole fraction value x = 0.3. The mole fraction value affects various electrical parameters in terms of leakage current, junction capacitance and transconductance of the channel region. The device exhibits reduced switching capacitance due to the smaller-bandgap pocket region between the source and channel. Analysis of the JLSGTFET is carried out for DC and AC parameters at room temperature. Temperature analysis plays a vital role in determining reliable ON- and OFF-state performance in transistors. Therefore, the proposed pocket JLSGTFET is investigated under harsh temperature conditions to characterize the performance for DC and subthreshold parameters. The sensitivity of the device is analyzed under different temperature conditions over a range of 250–400 K to observe subthreshold performance including transfer characteristics, output characteristics, ION/IOFF ratio, subthreshold slope (SS) and drain-induced barrier lowering (DIBL). The JLSGTFET demonstrates a small variation in DC and subthreshold parameters, indicating good prospects for future analog and digital applications. All the analysis of the proposed JLSGTFET is carried out on a 2D/3D VisualTCAD device simulator.

Self-biased nano-power four-transistor current and voltage reference with a single resistor

Abstract: A generic nano-power voltage and current reference topology, which takes advantage of the unequal threshold voltage ( V TH ) of two MOSFETs in subthreshold region, is developed to provide reliable bias and reference signals for the analogue integrated blocks used in the Internet-of-Things applications. The new architecture is a self-powered four-transistor topology with a single temperature-insensitive resistor, generating both temperature-independent voltage and current without any operational amplifier or bias network. Instead, the resistor defines the absolute value of the current reference ( I REF ) which supplies the core devices. The circuit is designed and simulated for a target current reference of 7.50 nA in 0.18 µm CMOS process, and achieves a worst-case temperature coefficient (TC) of 59.47 ppm/°C over a temperature range from −40 to 125°C and 1.8 V voltage supply. The average voltage reference ( V REF ) is 346 mV, and the worst-case TC of different corners is 21.98 ppm/°C. The nominal current consumption is twice the I REF (15 nA) regardless of the supply and temperature, and can be scaled down by reducing the desired current reference.

Set-reset latch logic operation in a bistable system under suprathreshold and subthreshold signals.

Abstract: A set–reset latch is a basic building block of computers and can be used to store state information. Here, by testing the influence of the two logical input signals on the reliable set–reset latch logic operation in the bistable system, we found that there are two types of input signals, namely, suprathreshold and subthreshold signals. For the suprathreshold signals, reliable set–reset logic operation can be achieved without any driving forces and exhibits certain anti-interference ability; for the subthreshold signals, a single harmonic could induce correct set–reset latch logic operation but with a narrow optimal parameter region. The introduction of biharmonic-induced set–reset latch logic operation (logical vibrational resonance) could greatly expand the parameter region. Explanations for the above results were provided by taking the logical inputs as the dynamic bias to analyze the dynamic changes in the system. Finally, the results were further verified by circuit simulation and actual hardware circuit.

Source pocket engineered underlap stacked-oxide cylindrical gate tunnel FETs with improved performance: design and analysis

Abstract: The effects of stacked SiO2/HfO2 gate oxide, source pocket, and underlap gate engineering on the electrical and RF performances of cylindrical gate tunnel field-effect transistors (CGTFETs) have been investigated in this paper. While source pocket with underlap engineering reduces both the gate leakage current and subthreshold swing (SS), the stacked gate oxide improves the drain current of the CGTFET. The DC and RF performance parameters such as the electric field, drain current, transconductance, gate capacitance, unity gain cut-off frequency, gain–bandwidth product, transconductance frequency product, and intrinsic delay have been investigated for different stacked oxide CGTFETs with and without a source pocket as well as with and without an underlap structure. Our study demonstrates that the proposed underlapped stacked-oxide source-pocket engineered CGTFET structure not only enhances the drain current, but also improves the subthreshold switching characteristics of the device by reducing SS and gate leakage current.

Design of Low Power Si 0.7 Ge 0.3 Pocket Junction-Less Tunnel FET Using Below 5 nm Technology

Abstract: This work proposed the design of low power Si0.7Ge0.3 pocket Junction-less TFET (JLTFET) on bulk silicon using below 5 nm technology. The inclusion of junction-less regions improves ON-state current with lesser effect on OFF-state current. The p-type pocket regions added to improve device performance in subthreshold region showing reduction in OFF-state leakage current leading to good value of ON/OFF current ratio as compared to other similar TFET structures. A high-value ION/IOFF ratio and good subthreshold behavior are observed for pocket JLTFET with 2 nm gate length and body thickness 0.5 nm. The proposed JLTFET is further optimized for different gate contact and oxide materials. The temperature analysis plays major role in deciding a reliable ON-state and OFF-state performance of transistors. So, the proposed pocket JLTFETis investigated for harsh temperature conditions to characterize the performance for DC and AC parameters. The sensitivity of proposed JLTFET is analyzed under different temperature conditions in range of (200–400) K to observe subthreshold performance such as transfer characteristics, Output characteristics and ION/IOFF ratio. The proposed designs for JLTFETs have been simulated using TCAD 2D/3D device simulator.

Central Role of Subthreshold Currents in Myotonia.

Abstract: It is generally thought that muscle excitability is almost exclusively controlled by currents responsible for generation of action potentials. We propose that smaller ion channel currents that contribute to setting the resting potential and to subthreshold fluctuations in membrane potential can also modulate excitability in important ways. These channels open at voltages more negative than the action potential threshold and are thus termed subthreshold currents. As subthreshold currents are orders of magnitude smaller than the currents responsible for the action potential, they are hard to identify and easily overlooked. Discovery of their importance in regulation of excitability opens new avenues for improved therapy for muscle channelopathies and diseases of the neuromuscular junction. ANN NEUROL 2020;87:175-183.

Fundamental Thermal Limits on Data Retention in Low-Voltage CMOS Latches and SRAM

Abstract: Ultra-low-power systems with substantial computing capacity require latches and SRAMs to operate at extremely low supply voltages. However, with aggressive technology scaling, reliability becomes a major challenge due to unavoidable process variations and the presence of multiple noise sources, including intrinsic thermal noise. This paper provides a quantitative measure of reliability by calculating the probability distribution function (PDF) of errors induced by thermal noise in latches and SRAMs operating in subthreshold conditions. Implemented in a novel simulation tool for thermal-noise analysis of CMOS circuits (STTACC), our algorithm uses a stochastic differential equation circuit model that preserves the proper Poissonian statistics for thermal-noise-driven current fluctuations in MOSFETs. Our probabilistic error model can handle error rate analysis for arrays of latches or full SRAMs on time scales from seconds to years without excessive computational overhead. We demonstrate that the time-to-error (TTE) statistics of subthreshold SRAMs obey log-normal distributions that depend on parameters such as node and device capacitance, device threshold variations and operating conditions of supply voltage and temperature. This makes it possible to quantitatively evaluate the asymptotic behavior of extremely rare error events that are inaccessible to standard SPICE-based simulations.

E-mode p-GaN Gate HEMT with p-FET Bridge for Higher V TH and Enhanced V TH Stability

Abstract: a novel p-GaN gate topology is proposed to inherently increase threshold voltage (V TH ) and enhance V TH stability. The gate consists of a conventional Schottky-type p-GaN gate and a normally-on p-channel FET bridge connecting source and gate. By modulating the V TH of the p-channel FET, a wide-range positive V TH from 3.6 V to 8.2 V can be achieved without subthreshold voltage degradation. Owing to the well-grounded p-GaN through the normally-on p-FET channel, a stable V TH is also achieved without sacrificing the low gate leakage and large gate swing enabled by the Schottky gate metal/p-GaN contact.