scispace - formally typeset
Search or ask a question
Topic

Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.


Papers
More filters
Journal ArticleDOI
TL;DR: In this article, the authors investigated the stochastic resonance in GaAs-based nanowire field effect transistors (FETs) controlled by Schottky wrap gate and their networks.
Abstract: Investigation of stochastic resonance in GaAs-based nanowire field-effect transistors (FETs) controlled by Schottky wrap gate and their networks is described. When a weak pulse train is given to the gate of the FET operating in a subthreshold region, the correlation between the input-pulse and source–drain current increases by adding input noise. Enhancement of the correlation is observed in a summing network of the FETs. Measured correlation coefficient of the present system can be larger than that in a linear system in the wide range of noise. An analytical model based on the electron motion over a gate-induced potential barrier quantitatively explains the experimental behaviors.

62 citations

Journal ArticleDOI
TL;DR: In this paper, a comparative study on the device design method of the sub-threshold slope and the threshold voltage control in fully-depleted silicon-on-insulator MOSFETs under sub-100-nm regime is presented.
Abstract: This paper presents the comparative study on the device design method of the subthreshold slope and the threshold voltage control in fully-depleted silicon-on-insulator MOSFETs under sub-100-nm regime. As for the threshold voltage adjustment method, the combination of the back gate bias and the gate work function controls is found to provide the superior short channel effects, the suppression of the threshold voltage fluctuation due to the SOI thickness variation, and the current drive improvement. As for the subthreshold slope, the importance and the necessity of buried oxide engineering are pointed out from the viewpoint of both the substrate capacitance and short-channel effects. It is shown, consequently, that the optimization of the thickness and the permittivity of buried oxides have a significant impact on the control of the subthreshold slope under sub-100-nm regime. When the gate length is less than 100 nm, the subthreshold slope has a minimum value at the buried oxide thickness of around 40 nm, irrespective of the SOI thickness. It is also shown that the reduction in the permittivity of the buried oxides under a constant buried oxide capacitance improves the subthreshold slope.

62 citations

Journal ArticleDOI
TL;DR: An analytical gate delay model is developed by integrating short-channel effects and the Alpha-power law-based timing model, which accurately predicts both nominal delay and delay variability over a wide range of power supply conditions including subthreshold and strong- inversion regions.
Abstract: An analytical gate delay model is developed by integrating short-channel effects and the Alpha-power law-based timing model. As verified with an industrial 90-nm technology, this analytical approach accurately predicts both nominal delay and delay variability over a wide range of power supply conditions including subthreshold and strong- inversion regions. Excellent model scalability enables efficient mapping between process variations and delay variability at the gate level. Based on this model, the impact of various physical effects on delay variability has been identified. While the variation of effective channel length is the leading source for delay variability at the current 90-nm node, delay variability is actually more sensitive to the variation of threshold voltage, especially in the subthreshold region. Furthermore, the limitation of low-power design techniques is investigated in the presence of process variations, particularly dual Vth and L biasing. These techniques become less effective at low VDD due to excessive delay variability.

62 citations

Journal ArticleDOI
TL;DR: A fracture mechanics model for subthreshold indentation flaws is described in this article, which describes the initiation and extension of a micro-crack from a discrete deformation-induced shear-fault (shear crack) within the contact zone.
Abstract: A fracture mechanics model for subthreshold indentation flaws is. described. The model describes the initiation and extension of a microcrack from a discrete deformation-induced shear “fault” (shear crack) within the contact zone. A stress-intensity factor analysis for the microcrack extension in residual-contact and applied-stress fields is used in conjunction with appropriate fracture conditions, equilibrium in Part I and non-equilibrium in Part II, to determine critical instability configurations. In Part I, the K-field relations are used in conjunction with the Griffith requirements for crack equilibrium in essentially inert environments to determine: (i) the critical indentation size (or load) for spontaneous radial crack pop-in from a critical shear fault under the action of residual stresses alone; (ii) the inert strengths of surfaces with subthreshold or postthreshold flaws. The theory is fitted to literature data for silicate glasses. These fits are used to “calibrate” dimensionless parameters in the fracture mechanics expressions, for later use in Part II. The universality of the analysis in its facility to predict the main features of crack initiation and propagation in residual and applied fields will be demonstrated. Special emphasis is placed on the capacity to account for the significant increase in strength (and associated scatter) observed on passing from the postthreshold to the subthreshold domain.

61 citations

Journal ArticleDOI
TL;DR: In this paper, a non-piecewise drain current model for long-channel junctionless (JL) cylindrical nanowire (CN) FETs is formulated by using the Pao-Sah integral and a continuous charge model.
Abstract: A nonpiecewise drain current model is formulated for long-channel junctionless (JL) cylindrical nanowire (CN) FETs It is obtained by using the Pao-Sah integral and a continuous charge model, which is derived by extending the parabolic potential approximation in all regions of the device operation The proposed nonpiecewise model analytically describes the bulk and surface current mechanisms in JL CN FETs from the subthreshold region through the linear region to the saturation region without any fitting parameters In addition, for each of these operation regions, the model reduces to simple expressions that explain the working principle of JL CN FETs The model is compared with numerical simulations and shows good agreement

61 citations


Network Information
Related Topics (5)
CMOS
81.3K papers, 1.1M citations
78% related
Transistor
138K papers, 1.4M citations
77% related
Integrated circuit
82.7K papers, 1M citations
75% related
Amplifier
163.9K papers, 1.3M citations
74% related
Field-effect transistor
56.7K papers, 1M citations
73% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023153
2022349
2021172
2020196
2019242
2018272