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Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.


Papers
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Journal ArticleDOI
TL;DR: In this article, a self-consistent contact block reduction (CBR) simulator has been used to simulate a 10-nm-FinFET device with channels along arbitrary crystallographic orientation.
Abstract: We have utilized the contact-block-reduction (CBR) method, which we extended to allow a charge self-consistent scheme, to simulate experimentally fabricated 10-nm-FinFET device. The self-consistent CBR simulator has been modified to simulate devices with channels along arbitrary crystallographic orientation. A series of fully quantum-mechanical transport simulations has been performed. First, the fin extension length and doping profile have been calibrated to match the experimental data. The process control window for the threshold voltage as a function of fin extension has been extracted for the considered device. Then, a set of transfer characteristics and gate leakage currents have been calculated for different drain voltages. The simulation results have been found to be in good agreement with the experimental data in the subthreshold regime. The device turn-off and turn-on behavior has been examined for different fin widths: 12 (experimental), 10, 8, and 6 nm. Finally, the subthreshold slope degradation at high temperatures has been studied

61 citations

Journal ArticleDOI
TL;DR: This work presents a biopotential front-end amplifier in which the MOS transistors are biased in subthreshold region with a supply voltage and current of 0.4-0.8 V and 0.23-1.86 μA, respectively, to reduce the system power.
Abstract: This work presents a biopotential front-end amplifier in which the MOS transistors are biased in subthreshold region with a supply voltage and current of 0.4-0.8 V and 0.23-1.86 μA, respectively, to reduce the system power. Flicker noise is then removed using a chopping technique, and differential interference produced by electrode impedance imbalance is suppressed using a Gm-C filter. Additionally, the circuit is fabricated using TSMC 0.18 μm CMOS technology with a core area of 0.77 × 0.36 mm2. With a minimum supply voltage of 0.4 V, the measured SNR and power consumption of the proposed IC chip are 54.1 dB and 0.09 μW , respectively.

61 citations

Book ChapterDOI
01 Dec 2008
TL;DR: In this article, the authors proposed the use of multiple gates to reduce the coupling between source and drain in the sub-threshold region and enable the multigate transistor to be scaled beyond bulk planar CMOS for a given dielectric thickness.
Abstract: The scaling of conventional planar CMOS is expected to become increasingly difficult due to increasing gate leakage and subthreshold leakage.[1-2] Multi-gate FETs such as FinFETs have emerged as the most promising candidates to extend the CMOS scaling into the sub-25nm regime.[3-4] The strong electrostatic control over the channel originating from the use of multiple gates reduces the coupling between source and drain in the subthreshold region and it enables the Multigate transistor to be scaled beyond bulk planar CMOS for a given dielectric thickness. Numerous efforts are underway to enable large scale manufacturing of multi-gate FETs. At the same time, circuit designers are beginning to design and evaluate multi-gate FET circuits.

61 citations

Journal ArticleDOI
TL;DR: In this paper, the inert strength and dynamic fatigue properties of fused-silica optical fibers are studied using sub-threshold indentation flaws, i.e., flaws without radial cracks.
Abstract: The inert strength and dynamic fatigue properties of fused-silica optical fibers are studied using subthreshold indentation flaws, i.e., flaws without radial cracks. These subthreshold properties differ from those obtained in comparative tests on silica rods containing postthreshold indentation flaws in three major respects: (1) the inert strengths are significantly higher than predicted by extrapolation of the postthreshold data; (2) the slopes of the dynamic fatigue plots are likewise greater, indicating a greater susceptibility of the subthreshold flaws to chemical kinetic effects; and (3) the scatter in strengths is wider. These trends reflect the change in mechanical response reported for optical fibers with “natural” flaw populations in going from ordinary to ultra-high-strength regions. Direct observations of the indentation sites up to the point of failure indicate that the property differences can be interpreted in terms of a transition from propagation-controlled to initiation-controlled fracture instabilities at reduced contact loads. The subthreshold instability condition is modeled qualitatively as a two-step, deformation-fracture process, with strong emphasis on the importance of residual stress fields in parametric evaluations. The relevance of the results to the practical issue of fiber reliability, most notably in connection with the potential dangers of using macroscopic crack velocity data to predict long-lifetime characteristics, is addressed.

61 citations

Journal ArticleDOI
Hans-Oliver Joachim1, Y. Yamaguchi1, K. Ishikawa1, Y. Inoue1, T. Nishimura1 
TL;DR: In this article, a modified boundary condition for the two-dimensional Poisson equation is introduced to account for the nonlinear potential distribution inside the buried oxide, and it is found that the S-factor short-channel degradation is governed by three mechanisms: the rise of capacitances at the channel source and drain ends due to the twodimensional potentional distribution; the subthreshold current flow at the back channel surface; and the modulation of the effective current channel thickness during the gate voltage swing in the sub-reshold region.
Abstract: The subthreshold slope in ultra-thin-film fully depleted SOI MOSFETs is investigated for channel lengths from the long channel region down to 0.1 mu m. A doping effect is found which allows improvement of the S-factor by increasing the channel doping concentration. In order to explain this phenomenon and to clarify the mechanism of S-factor degradation at short gate lengths, a two-dimensional analytical model is developed. A modified boundary condition for the two-dimensional Poisson equation is introduced to account for the nonlinear potential distribution inside the buried oxide. It is found that the S-factor short-channel degradation is governed by three mechanisms: the rise of capacitances at the channel source and drain ends due to the two-dimensional potentional distribution; the subthreshold current flow at the back channel surface; and the modulation of the effective current channel thickness during the gate voltage swing in the subthreshold region. The analytical model results are compared to those of numerical device simulation, and a good agreement is found. >

61 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023153
2022349
2021172
2020196
2019242
2018272