Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS

Abstract: While the general trend in CMOS technology scaling is mostly focused on high-performance and high-speed circuits, the potential use of advanced nanoscale technologies for ultra-low power (ULP) applications with lower operating frequencies is still debated. In these types of applications, the supply voltage is generally reduced well below threshold voltage of MOS devices in order to limit dissipation and to control the device leakage current due to the subthreshold channel residual current. However, recent studies show that reducing the supply voltage increases the device susceptibility to process variations, resulting in delay spread and decreased noise margin. This article presents an analytical approach for studying the effect of technology scaling and variability on performance of ULP integrated systems. Unlike the conventional design methodologies, we include the effect of process variation on circuit performance (such as on noise margin and delay) in each step of design and optimization. Here, the power dissipation and noise margin are both calculated as a function of turn-on and turn-off current of devices. This approach helps to explore the effect of these two quantities on performance of CMOS digital circuits. The trade-offs between the choice of supply voltage, threshold voltage, device dimensions, delay performance, activity rate, and power consumption are analytically examined using predictive device models, for different technology nodes. Taking into account the circuit reliability requirements, this analysis can be used to optimize the system performance with proper device sizing and selecting supply voltage.

The most likely voltage path and large deviations approximations for integrate-and-fire neurons

Abstract: We develop theory and numerical methods for computing the most likely subthreshold voltage path of a noisy integrate-and-fire (IF) neuron, given observations of the neuron’s superthreshold spiking activity. This optimal voltage path satisfies a second-order ordinary differential (Euler-Lagrange) equation which may be solved analytically in a number of special cases, and which may be solved numerically in general via a simple “shooting” algorithm. Our results are applicable for both linear and nonlinear subthreshold dynamics, and in certain cases may be extended to correlated subthreshold noise sources. We also show how this optimal voltage may be used to obtain approximations to (1) the likelihood that an IF cell with a given set of parameters was responsible for the observed spike train; and (2) the instantaneous firing rate and interspike interval distribution of a given noisy IF cell. The latter probability approximations are based on the classical Freidlin-Wentzell theory of large deviations principles for stochastic differential equations. We close by comparing this most likely voltage path to the true observed subthreshold voltage trace in a case when intracellular voltage recordings are available in vitro.

Novel strong PUF based on nonlinearity of MOSFET subthreshold operation

Abstract: Many strong silicon physical unclonable functions (PUFs) are known to be vulnerable to machine-learning attacks due to linear separability of the output function. This significantly limits their potential as reliable security primitives. We introduce a novel strong silicon PUF based on the exponential current-voltage behavior in subthreshold region of FET operation which injects strong nonlinearity into the response of the PUF. The PUF, which we term subthreshold current array (SCA) PUF, is implemented as a pair of two-dimensional n × k transistor arrays with all devices subject to stochastic variability operating in subthreshold region. Our PUF is fundamentally different from earlier attempts to inject nonlinearity via digital control techniques, which could also be used with SCA-PUF. Voltages produced by nominally identical arrays are compared to produce a random binary response. SCA-PUF shows excellent security properties. The average inter-class Hamming distance, a measure of uniqueness, is 50.2%. The average intra-class Hamming distance, a measure of response stability, is 4.17%. Crucially, we demonstrate that the introduced PUF is much less vulnerable to modeling attacks. Using machine-learning techniques of support-vector machine with radial basis function kernel and logistic regression for best nonlinear learnability, we observe that “information leakage” (rate of error reduction with learning) is much lower than for delay-based PUFs. Over a wide range of the number of observed challenge-response pairs, the error rate is 3-35X higher than for the delay-based PUF. We also demonstrate an enhanced SCAPUF design utilizing XOR scrambling and show that it has an up to 30X higher error rate compared to the XOR delay-based PUF.

Temperature sensing circuit

Abstract: A temperature sensing circuit has a first insulated gate field effect device which is operated deep into its subthreshold region where the voltage across the device varies with temperature and has a second insulated gate field effect device which is operated in an area of its square law region where the voltage across the second insulated gate field effect device is substantially independent of temperature. A comparator compares the voltages across the first and second field effect devices and provides a signal OT indicating the temperature sensed by the first insulated gate field effect device.