Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

A Wideband 2–5 GHz Noise Canceling Subthreshold Low Noise Amplifier

Abstract: This brief presents an energy efficient wideband low noise amplifier (LNA) operating in subthreshold regime. Wideband matching and low noise figure in subthreshold domain is achieved by using a gate inductor-assisted impedance matching and a current reuse feed-forward noise cancelation technique, respectively. Fabricated in UMC 0.18- $ {\mu }\text{m}$ CMOS technology, the proposed LNA draws 1 mA from 1.8-V supply and achieves a voltage gain of 13 dB (taking into account a 8 dB loss in buffer), minimum noise figure ( ${\text {NF}}_{\text {min}}$ ) of 6 dB, and 3 dB bandwidth from 2 to 5 GHz.

Demonstration of scaled Ge p-channel FinFETs integrated on Si

Abstract: We report the first demonstration of scaled Ge p-channel FinFET devices fabricated on a Si bulk FinFET baseline using the Aspect-Ratio-Trapping (ART) technique [1] Excellent subthreshold characteristics (long-channel subthreshold swing SS=76mV/dec at 05V), good SCE control and high transconductance (12 mS/μm at 1V, 105 mS/μm at 05V) are achieved The Ge FinFET presented in this work exhibits highest g m /SS at V dd =1V reported for non-planar unstrained Ge pFETs to date

Subthreshold Analog/RF Performance Enhancement of Underlap DG FETs With High- K Spacer for Low Power Applications

Abstract: This paper presents a systematic study of the subthreshold analog/RF performance for underlap double gate (UDG) NMOSFETs using high dielectric constant (k) spacers. The conventional UDG-NMOSFETs offer reduced short-channel effects along with improved subthreshold analog/RF performance at a cost of higher distributed channel resistance and low on current. In this paper, we show that these drawbacks can be alleviated effectively by using high-k spacers without any severe degradation in the subthreshold analog/RF performance. In order to show the improvement in the device performance, we have studied the effect of high-k spacers on different subthreshold analog figures of merit such as the transconductance, transconductance generation factor, output resistance, and the intrinsic gain for different values of k . Moreover, we have analyzed the RF performance as a function of intrinsic capacitance and resistance, transport delay, inductance, cutoff frequency, and the maximum oscillation frequency. In order to assess the gain bandwidth (GBW) product, the circuit implementation of the UDG-NMOSFETs with different high-k spacers was performed on a common source amplifier. Our results show an improvement in the GBW of about 38% for the devices with high- k spacers compared to its low- k counterpart.

A p-channel MOS synapse transistor with self-convergent memory writes

Abstract: We have developed a p-channel floating-gate-MOS synapse transistor for silicon-learning applications. The synapse stores a nonvolatile analog weight by means of charge on its floating gate, modifies this weight bidirectionally using electron tunneling and hot-electron injection, and allows simultaneous memory reading and writing. The synapse also learns locally-its weight updates depend only on the applied terminal voltages and on the stored weight. We fabricated an array of synapses that computed both the array output, and the weight updates, in parallel. We also demonstrated a self-convergent write procedure that permitted accurate initialization of the synapse weights. Our pFET synapse is small, and is operated at subthreshold current levels; it will permit the development of dense, low-power, silicon learning systems.