Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Precise Modeling Framework for Short-Channel Double-Gate and Gate-All-Around MOSFETs

Abstract: A precise modeling framework for short-channel nanoscale double-gate (DG) and gate-all-around (GAA) MOSFETs is presented. For the DG MOSFET, the modeling is based on a conformal mapping analysis of the potential distribution in the device body arising from the interelectrode capacitive coupling, combined with a self-consistent procedure to include the effects of the inversion charge. The DG interelectrode coupling, which dominates the subthreshold behavior of the device, can also be applied with a high degree of precision to the cylindrical GAA MOSFET by performing a simple geometric scaling transformation to account for the difference in gate control in the two devices. Near threshold, self-consistent procedures invoking Poisson's equation in combination with boundary conditions and suitable modeling expressions for the potential are applied to the two devices. In strong inversion, these solutions converge to those of the respective long-channel devices. The drain current is calculated as part of the self-consistent treatment. The results for both the electrostatics and the current are in excellent agreement with numerical simulations.

Subthreshold membrane currents confer distinct tuning properties that enable neurons to encode the integral or derivative of their input

Abstract: Neurons rely on action potentials, or spikes, to encode information. But spikes can encode different stimulus features in different neurons. We show here through simulations and experiments how neurons encode the integral or derivative of their input based on the distinct tuning properties conferred upon them by subthreshold currents. Slow-activating subthreshold inward (depolarizing) current mediates positive feedback control of subthreshold voltage, sustaining depolarization and allowing the neuron to spike on the basis of its integrated stimulus waveform. Slow-activating subthreshold outward (hyperpolarizing) current mediates negative feedback control of subthreshold voltage, truncating depolarization and forcing the neuron to spike on the basis of its differentiated stimulus waveform. Depending on its direction, slow-activating subthreshold current cooperates or competes with fast-activating inward current during spike initiation. This explanation predicts that sensitivity to the rate of change of stimulus intensity differs qualitatively between integrators and differentiators. This was confirmed experimentally in spinal sensory neurons that naturally behave as specialized integrators or differentiators. Predicted sensitivity to different stimulus features was confirmed by covariance analysis. Integration and differentiation, which are themselves inverse operations, are thus shown to be implemented by the slow feedback mediated by oppositely directed subthreshold currents expressed in different neurons.

Challenges and design choices in nanoscale CMOS

Abstract: The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In this article, we will first review the history of technology scaling that follows Moore's law from the prespective of microprocessor designs. Challenges to continue the historical scaling trends will be highlighted and design choices to address two specific challenges, process variation and leakage power, will be discussed. In nanoscale CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. One such challenge is the expected increase in process variation and the resulting increase in design margins. Concept of adaptive circuit schemes to deal with increasing design margins will be explained. Next, with threshold voltage scaling, subthreshold leakage power has become a significant portion of total power in nanoscale CMOS systems. Therefore, it has become imperative to accurately predict and minimize leakage power of such systems, especially with increasing within-die threshold voltage variation. A model that predicts system leakage based on first principles will be presented and circuit techniques to reduce system leakage will be discussed. It is essential to point out that this article does not cover all challenges that nanoscale CMOS systems face. Challenges that are not detailed in the main sections of the article and speculation on what future nanoscale silicon based CMOS systems might resemble are summarized.

20.3 A 100nA-to-2mA successive-approximation digital LDO with PD compensation and sub-LSB duty control achieving a 15.1ns response time at 0.5V

Abstract: Modern subthreshold SoC designs feature multiple power domains to dynamically track the maximum energy-efficiency point (0.32–0.45V [1]) in response to application demands. While analog low-drop-out (LDO) regulators have shown rapid response times (e.g. T R = 0.65ns [2]) and excellent steady-state performance, they fail to operate at the low input voltages, V IN , typically supplied to such SoCs via either a high-efficiency switching DC-DC converter or an external harvesting source (e.g., V IN = 0.5V). On the other hand, digital LDOs (DLDOs) are becoming popular in low-voltage SoC designs where they can operate reliably from supplies down to 0.5V. However, conventional DLDOs respond slowly to large current steps, especially at low voltages (e.g., T R = ∼44ns, 57.1ns, and 4µs at V IN =1V [3–5], and 20µs at V IN =0.5V [1]). Furthermore, they suffer from limited dynamic range over which the load is regulated and stable (e.g. s , this comes at increased power consumption and, importantly, reduced loop stability. To address these issues, this paper presents a 0.5V 0.0023mm2 recursive all-digital LDO (RLDO) in 65nm with hybrid PD-SAR and PWM duty control that achieves 15.1ns and 100ns response and settling times, respectively, while maintaining 5.6mV/mA load regulation and loop stability across a 20,000× dynamic load range, eclipsing state-of-the-art active area, response time, settling time, and dynamic range metrics across prior-art digital LDOs by over an order of magnitude.