Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Subthreshold leakage modeling and reduction techniques [IC CAD tools]

Abstract: As technology scales, subthreshold leakage currents grow exponentially and become an increasingly large component of total power dissipation. CAD tools to help model and manage subthreshold leakage currents will be needed for developing ultra low power and high performance integrated circuits. This paper gives an overview of current research to control leakage currents, with an emphasis on areas where CAD improvements will be needed. The first part of the paper explores techniques to model subthreshold leakage currents at the device, circuit, and system levels. Next, circuit techniques such as source biasing, dual V/sub t/ partitioning, MTCMOS, and VTCMOS are described. These techniques reduce leakage currents during standby states and minimize power consumption. This paper also explores ways to reduce total active power by limiting leakage currents and optimally trading off between dynamic and leakage power components.

An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement

Abstract: We propose a technique for improving write margin and read performance of 8T subthreshold SRAMs by using long channel devices to utilize the pronounced reverse short channel effect. Simulations show that the proposed cell at 0.2 V has a write margin equivalent to a conventional cell at 0.27 V. The Ion-to-Ioff ratio of the read path also improved from 169 to 271 and a 52% speedup for read was achieved. The cell area overhead was 20%.

Room temperature 0.1 /spl mu/m CMOS technology with 11.8 ps gate delay

Abstract: We report a room temperature, 0.1 /spl mu/m CMOS technology on bulk Si substrates that delivers a record ring-oscillator gate delay of 11.8 psec at 2.5 V. Frequency dividers at 2.0 V operate with input frequencies exceeding 8.5 GHz. Feature sizes obey g-line lithography design rules except at the gate level. The high speed CMOS performance and the good subthreshold and drain characteristics for both NMOS and PMOS devices are obtained through the implementation of vertical doping engineering and the reduction of parasitics. >

Oscillations emerging from noise-driven steady state in networks with electrical synapses and subthreshold resonance

Abstract: Oscillations play a critical role in cognitive phenomena and have been observed in many brain regions. Experimental evidence indicates that classes of neurons exhibit properties that could promote oscillations, such as subthreshold resonance and electrical gap junctions. Typically, these two properties are studied separately but it is not clear which is the dominant determinant of global network rhythms. Our aim is to provide an analytical understanding of how these two effects destabilize the fluctuation-driven state, in which neurons fire irregularly, and lead to an emergence of global synchronous oscillations. Here we show how the oscillation frequency is shaped by single neuron resonance, electrical and chemical synapses.The presence of both gap junctions and subthreshold resonance are necessary for the emergence of oscillations. Our results are in agreement with several experimental observations such as network responses to oscillatory inputs and offer a much-needed conceptual link connecting a collection of disparate effects observed in networks.