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Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.


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Journal ArticleDOI
TL;DR: In this article, a p-n-i-n TFET with vertical pocket at the source-channel junction is compared with a line tunneling TFET, containing horizontal pockets in the source region.
Abstract: The tunnel field-effect transistor (TFET) is a promising candidate to replace the metal-oxide-semiconductor field-effect transistor in advanced technology nodes, because of its potential to obtain sub-60 mV/dec subthreshold swings. However, it is challenging to reach sufficiently high on-currents in TFETs. Therefore, on-current boosters are actively being researched. In this paper, a p-n-i-n TFET, containing a vertical pocket at the source-channel junction, is studied with quantum mechanical simulations and compared with a line tunneling TFET, containing horizontal pockets in the source region. The comparison is carried out both for all-Si and all-Ge, while an extrapolation is made for smaller bandgap materials. The p-n-i-n TFET is found to perform better than a p-i-n configuration, thanks to the increased electric field at the source-pocket junction. Compared to the p-n-i-n TFET, the line TFET has an even higher on-current and lower subthreshold swing, attributed to the closer proximity of the tunnel junction to the gate. For the all-Ge case, the difference between the two configurations is found to decrease when direct transitions are taken into account semi-classically.

52 citations

Proceedings ArticleDOI
03 Jan 2005
TL;DR: An accurate and efficient stacking effect macro-model for leakage power in sub-100 nm circuits is presented, making use of the interactions between subthreshold leakage and gate leakage and proposing a new best input vector to reduce the total leakage power.
Abstract: An accurate and efficient stacking effect macro-model for leakage power in sub-100 nm circuits is presented in this paper. Leakage power, including subthreshold leakage power and gate leakage power, is becoming more significant compared to dynamic power when technology scaling down below 100 nm. Consequently, fast and accurate leakage power estimation models, which are strongly dependent on precise modeling of the stacking effect on subthreshold leakage and gate leakage, are vital for evaluating optimizations. In this work, making use of the interactions between subthreshold leakage and gate leakage, we focus our attention on analyzing the effects of transistor stacking on gate leakage between the channel and the gate and that between the drain/source and the gate. The contribution of the latter has been largely ignored in prior work, while our work shows that it is an important factor. Based on the stacking effect analysis, we have proposed a new best input vector to reduce the total leakage power; and an efficient and accurate leakage power estimation macro-model which achieves a mean error of 3.1% when compared to HSPICE.

52 citations

Journal ArticleDOI
TL;DR: In this paper, the temperature dependence of transistor mismatch in a 65-nm CMOS platform over a temperature range of 0degC to 125degC was studied, and it was shown that the relative-current-mismatch fluctuation properties improve marginally in strong inversion, while they are strongly affected in the subthreshold region.
Abstract: We present a study of the temperature dependence of transistor mismatch in a 65-nm CMOS platform over a temperature range of 0degC to 125degC. We show that the relative-drain-current-mismatch fluctuation properties improve marginally in strong inversion, while they are strongly affected in the subthreshold region. This is compared and explained with a commonly used model. Furthermore, we analyze the change over temperature of the ION mismatch of individual matched pairs. This analysis shows, for the first time, that although relative-current-mismatch fluctuation standard deviations estimated on whole populations are reduced at higher temperatures, the current mismatch of individual pairs can change substantially over temperature.

52 citations

Journal ArticleDOI
TL;DR: In this paper, the authors presented an analysis of electrical noise in III-V heterojunction TFET (HTFET) using numerical simulations, and found that HTFET RTN amplitude does not scale inversely with gate length and is governed by tunneling distance of carriers at source-channel junction.
Abstract: We present an analysis of electrical noise in III-V heterojunction TFET (HTFET) Using numerical simulations, random telegraph noise (RTN) amplitude induced by a single charge trap is investigated with regard to trap location, electron band-to-band-generation rate, bias, and transistor size It is found that HTFET RTN amplitude does not scale inversely with gate length and is governed by tunneling distance of carriers at source-channel junction HTFET exhibits 40% less relative RTN amplitude at 03 V at gate lengths around 20 nm, over subthreshold Si-FinFET RTN of HTFET at VGS=0 V is higher for a trap location at source-channel tunnel junction To analyze flicker, shot, and thermal noise, we created transistor level Verilog-A-based electrical noise models The results indicate HTFETs competitive noise performance in megahertz frequency range, over Si-FinFET In the range 10 GHz or more with operating voltages exceeding 03 V, HTFET input noise is worse due to the dominance of shot noise A differential amplifier with active load is used to examine the electrical noise performance at circuit level We emphasize that high intrinsic gain, drive current, and output resistance of HTFET can be used to achieve superior mixed signal performance metrics in HTFET design over Si-FinFET design, at an improved electrical noise performance

52 citations

Journal ArticleDOI
TL;DR: Psychiatric comorbidities and health‐care utilization are common among patients with subthreshold panic, and the relationship between varying degrees of panic symptomology and other mental health problems and indices of functioning impairment warrants further investigation.
Abstract: Background: Panic disorder (PD) is a highly prevalent and disabling condition, and subthreshold cases may be even more prevalent. This study examined psychiatric comorbidities, work functioning, and health-care utilization of individuals with subthreshold panic. The purpose of this study was to add to the accumulating evidence of significant comorbidity and disability associated with subthreshold PD. Methods: Data are drawn from the Health Care for Communities study, a national household survey of the United States' adult, civilian, noninstitutionalized population (N=9585). Data assessing psychiatric disorders, employment and work productivity, and health-care utilization were collected. Seven categories of panic and subthreshold panic were created. Results: The prevalence of clinical and subthreshold panic in the general population was 40%. Subthreshold panic was associated with increased odds of several comorbid disorders, including depression, dysthymia, psychosis, generalized anxiety disorder, bipolar disorder, and alcohol and drug use disorders. Subthreshold panic was also associated with greater likelihood of health-care service utilization but not with the intensity of mental health services. Conclusion: Psychiatric comorbidities and health-care utilization are common among patients with subthreshold panic. The relationship between varying degrees of panic symptomology and other mental health problems and indices of functioning impairment warrants further investigation. These results inform further research focusing on the course of subthreshold PD and its impact on quality of life. Depression and Anxiety, 2010. © 2009 Wiley-Liss, Inc.

52 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023153
2022349
2021172
2020196
2019242
2018272