Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

“Hump” characteristics and edge effects in polysilicon thin film transistors

Abstract: Transfer characteristics of polycrystalline silicon (polysilicon) thin film transistors (TFTs) often show a “hump” in subthreshold regime. This effect, also observed in silicon-on-insulator (SOI) transistors, can be attributed to the presence of an enhanced electrical field at edges of the channel, which is related to the specific shape of the edge and its surrounding oxide. In this paper we attempt an analysis of the hump effect in polysilicon TFTs combining electrical measurements and two dimensional numerical simulations, and considering several geometries of the channel edge. The transfer characteristics showing the hump effect are analyzed in terms of a parallel of the main (“bulk”) transistor with two parasitic transistors located at the channel edges. The main and parasitic transistors have different threshold voltages and subthreshold swings and the equivalent parallel circuit reproduces very well the experimental transfer characteristics. The effect on the hump of interface states and oxide fixed...

Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation

Abstract: In this paper, the classical CMOS Schmitt trigger (ST) operating in the subthreshold regime is analyzed. The complete DC voltage transfer characteristic of the CMOS ST is determined. The metastable segment of the characteristic is explained in terms of the negative resistance of the NMOS and PMOS subcircuits of the ST. Small-signal analysis is carried out to determine the minimum supply voltage at which the hysteresis appears and to obtain a rough estimation of the hysteresis width. It is shown that the theoretical minimum supply voltage required to obtain hysteresis is 2ln( $2+\surd 5$ )kT/q = 75 mV at room temperature. A test chip with CMOS Schmitt triggers was designed and fabricated in a 180 nm technology in order to study their operation at supply voltages between 50 mV and 1000 mV.

A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS

Abstract: High-throughput parallel SIMD vector computations are the most performance and power-critical operations in multimedia, graphics and signal processing workloads. An array of SIMD vector processing engines delivers high-throughput short bit-width arithmetic operations on large data sets with orders of magnitude higher energy efficiencies vs. general-purpose cores [1, 2]. A reconfigurable 4-way SIMD engine targeted for on-die acceleration of vector processing in power-constrained mobile microprocessors is fabricated in 45nm High-K/Metal-gate CMOS [3]. The accelerator is reconfigured to perform 4-way 16b×16b multiplies, 32b×32b multiply, 4-way 16b additions, 2-way 32b additions and 72b addition with single-cycle throughput and wide dynamic supply voltage range of operation (1.3V to 230mV). A reconfigurable 2×2 tile of signed 2's complement 16b multipliers, with conditional carry gating in the 72b sparse tree adder, dual-supplies for voltage hopping, and fine-grained power-gating enables peak energy efficiency of 494GOPS/W (measured at 300mV, 50°C) with a dense layout occupying 0.081mm2 (Fig. 14.6.7) while achieving: (i) scalable performance up to 2.8GHz, 278mW measured at 1.3V, (ii) fast single-cycle switching between any operating/idle mode, (iii) configuration-dependent power consumption with 41% total power reduction and 6.5× active leakage power savings, (iv) 10× standby leakage reduction during sleep mode, (v) deep subthreshold operation measured at 230mV, 8.8MHz, 87µW, and (vi) compensation for up to 3× performance variation in ultra-low voltage mode.

A 6b 0.2-to-0.9V Highly Digital Flash ADC with Comparator Redundancy

Abstract: Microsensor wireless networks and implanted biomedical devices have emerged as exciting new application domains. These applications are highly energy constrained and require flexible, integrated, energy-efficient ADC modules that can ideally operate at the same supply voltage as digital circuits. In many applications, the performance requirements are quite modest (100s kS/s). This paper presents a highly digital ADC architecture compatible with advanced CMOS processes, capable of operating down to a supply voltage of 200mV (i.e., subthreshold regime) and up to 900mV. However, leakage and device variation must be addressed, particularly at low supply voltages.

Role of self-assembled monolayer passivation in electrical transport properties and flicker noise of nanowire transistors.

Abstract: Semiconductor nanowires have achieved great attention for integration in next-generation electronics. However, for nanowires with diameters comparabletotheDebyelength,whichwouldgenerally berequiredforone-dimensionaloperation,surfacestatesdegradethedeviceperformanceand increase the low-frequency noise. In this study, single In2O3 nanowire transistors were fabricated and characterized before and after surface passivation with a self-assembled monolayer of1-octadecanethiol(ODT).Electrical characterization ofthetransistorsshowsthat device performance can be enhanced upon ODT passivation, exhibiting steep subthreshold slope (∼64 mV/dec), near zero threshold voltage (∼0.6 V), high mobility (∼624 cm 2 /V 3 s), and high on-currents (∼40 μA). X-ray photoelectron spectroscopy studies of the ODT- passivated nanowires indicate that the molecules are bound to In2O3 nanowires through the thiol linkages. Device simulations using a rectangular geometry to represent the nanowire indicate that the improvement in subthreshold slope and positive shift in threshold voltage can be explained in terms of reduced interface trap density and changes in fixed charge density. Flicker (low-frequency, 1/f) noise measurements show that the noise amplitude is reduced following passivation. The interface trap density before and after ODT passivation is profiled throughout the band gap energy using the subthreshold currentvoltage character- istics and is compared to the values extracted from the low-frequency noise measurements. The results indicate that self-assembled monolayer passivation is a promising optimization technologyfortherealizationoflow-power,low-noise,andfast-switchingapplicationssuchas logic, memory, and display circuitry.