Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Semiconductor integrated circuit having a stand-by current reducing circuit

Abstract: A device parameter of a switching transistor is set in such a way that a leakage current of the switching transistor making up a power source switch which is turned off in a stand-by state is smaller than the sum total of subthreshold currents of P-channel or N-channel MOS transistors in an off state of a plurality of CMOS circuits. Therefore, the currents which flow through the plurality of CMOS circuits in the stand-by state are not determined by the subthreshold current but are determined by a small leakage current of the switching transistor. As a result, even when the CMOS circuit is shrunken and the subthreshold current increases, it is possible to reduce the current consumption in the stand-by state.

Charge-pumping characterization of SiO/sub 2//Si interface in virgin and irradiated power VDMOSFETs

Abstract: The applicability of charge-pumping technique to characterize the oxide/silicon interface in standard power Vertical Double-diffused (VD)MOS transistors is studied. Qualitative analysis of the charge-pumping threshold and flat-band voltage distributions in the VDMOS structure, supported with rigorous transient numerical modeling of the charge-pumping effect, shows that the measurements can be carried out in the subthreshold region. This conclusion is confirmed by various experimental results. The characteristics, i.e. charge-pumping current versus gate top level, is studied in detail. The changes in the characteristics after /spl gamma/-ray irradiation are analyzed. A charge-pumping-based method for separate extraction of interface state density and density of charge trapped in the oxide after irradiation of VDMOSFETs is proposed. The validity and limitations of the method are studied by experiments and modeling.

A compact drain current model of short-channel cylindrical gate-all-around MOSFETs

Abstract: A fully analytical potential model, valid in the weak inversion regime of short-channel cylindrical gate-all-around (GAA) MOSFET, is proposed. The model derivation is based on a previous analytical expression for tetragonal GAA MOSFET and the rotational symmetry of the tetragonal cross section. Device simulations were performed to verify that the potential distribution along the channel is properly described in all positions within the silicon body. Using the potential model, analytical expressions for the threshold voltage, subthreshold swing and drain-induced barrier lowering have been derived. Including the short-channel effects within an existing model for the subthreshold leakage current and an analytical drain current model of long-channel devices in strong inversion, a compact drain current model has been derived describing with good accuracy the transfer and output characteristics of short-channel GAA MOSFETs in all regions of operation.

An Energy Efficient Parallel Architecture Using Near Threshold Operation

Abstract: Subthreshold circuit design, while energy efficient, has the drawback of performance degradation. To retain the excellent energy efficiency while reducing performance loss, we propose to investigate near subthreshold techniques on chip multiprocessors (CMP). We show that logic and memory cells have different optimal supply and threshold voltages, therefore we propose to allow the cores and memory to operate in different voltage regions. With the memory operating at a different voltage, we then explore the design space in which several slower cores clustered together share a faster LI cache. We show that an architecture such as this is optimal for energy efficiency. In particular, SPLASH2 benchmarks show a 53% energy reduction over the conventional CMP approach (70% energy reduction over a single core machine). In addition we explore the design trade-offs that occur if we have a separate instruction and data cache. We show that some applications prefer the data cache to be clustered while the instruction cache is kept private to the core allowing further energy savings of a 77% reduction over a single core machine.