Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Binding by Asynchrony: The Neuronal Phase Code

Abstract: Neurons display continuous subthreshold oscillations and discrete action potentials. When action potentials are phase-locked to the subthreshold oscillation, we hypothesize they represent two types of information: the presence/absence of a sensory feature and the phase of subthreshold oscillation. If subthreshold oscillation phases are neuron-specific, then the sources of action potentials can be recovered based on the action potential times. If the spatial information about the stimulus is converted to action potential phases, then action potentials from multiple neurons can be combined into a single axon and the spatial configuration reconstructed elsewhere. For the reconstruction to be successful, we introduce two assumptions: that a subthreshold oscillation field has a constant phase gradient and that coincidences between action potentials and intracellular subthreshold oscillations are neuron-specific as defined by the "interference principle." Under these assumptions, a phase coding model enables information transfer between structures and reproduces experimental phenomenons such as phase precession, grid cell architecture, and phase modulation of cortical spikes. This article reviews a recently proposed neuronal algorithm for information encoding and decoding from the phase of action potentials (Nadasdy 2009). The focus is given to the principles common across different systems instead of emphasizing system specific differences.

Optimal Design Methods to Transform 3D NAND Flash into a High-Density, High-Bandwidth and Low-Power Nonvolatile Computing in Memory (nvCIM) Accelerator for Deep-Learning Neural Networks (DNN)

Abstract: We propose optimal design methods of 3D NAND Flash to achieve high-density, high-bandwidth and low-power nvCIM. By suitably engineering the device, we can produce ultra-low ON current of 2nA (mean) at saturated region instead of subthreshold region, while the OFF leakage current is much below 1pA. Such low Ion and large ON/OFF ratio provide large bandwidth to parallelly sum more than 10’000 cells together to offer high efficiency for DNN computing. The three-dimensional summation in 3D NAND also allows effective multi-bit resolution of weight without resorting to complex analog memory design. For the first time we witnessed the power of "central limit theory" in 3D NAND nvCIM, where the large number of summation averages out the noise and provides high accuracy of MAC. The effect of non-ideal cell variations, noises and shifts are studied systematically. Through adequate calibration techniques the 3D NAND nvCIM can provide accuracy close to the software limitation, with reasonable tolerance to various device errors. The 3D NAND nvCIM is promising to be an energy-efficient (TOPS/W~40) edge computing solution for large neural networks (>100Mb weight).

A Two-Dimensional Analytical Solution for Short-Channel Effects in Nanowire MOSFETs

Abstract: This brief presents an analytical solution of the electrostatic potential for nanowire MOSFETs in the subthreshold region by solving Poisson's equation in two dimensions (2D) in both semiconductor and gate insulator regions under cylindrical coordinates. Combining the analytical solution with the current continuity equation, one can derive an expression for the subthreshold current, from which the important parameters for short-channel effects (SCEs), such as threshold voltage rolloff, drain-induced barrier lowering, and subthreshold slope degradation, are analytically extracted. The 2D analytical model for SCEs has been validated by the numerical simulation results.

Biasing CMOS amplifiers using MOS transistors in subthreshold region

Abstract: The implementation of large-valued floating resistive elements using MOS transistors in subthreshold region is addressed. The application of these elements to bias wideband AC coupled amplifiers is discussed. Simple schemes to generate the gate control voltages for the MOS transistors implementing large resistors so that they remain in high resistive state with large signal variations are discussed. Experimental results of a test chip prototype in 0.5-µm CMOS technology are presented that verify the proposed technique.

Physical models for amorphous-silicon thin-film transistors and their implementation in a circuit simulation program

Abstract: A semianalytic theory to describe both the current-voltage and capacitance-voltage characteristics of amorphous silicon thin-film transistors on the basis of their physics of operation is presented. In this model, the drain current is directly related to the electron concentration at the source side of the channel. This enables one to describe the various regimes of operation of these devices (i.e. subthreshold or above threshold) using only one equation. The output conductance of these devices in saturation is also considered, and it is shown that the finite output impedance is a consequence of the drain voltage modulating the effective channel length by creating a space-charge limited current region of variable length near the drain. The results of this model are in good agreement both with experimental data and the results of comprehensive two-dimensional simulations. These device models have been successfully incorporated into a SPICE circuit simulation program. >