Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Computational Study on the Performance of Si Nanowire pMOSFETs Based on the $k \cdot p$ Method

Abstract: Full-quantum device simulations on p-type Si nanowire field-effect transistors based on the k · p method, using the k ·p parameters tuned against the sp3s* tight-binding method, are carried out. Full transport calculations from both methods agree reasonably well, and the spin-orbit coupling effect is found to be negligible in the final current-voltage characteristics. Use of the highly efficient simulator based on the 3 × 3 k ·p Hamiltonian is therefore justified, and simulations of nanowire devices with cross sections from 3 × 3 nm2 up to 10 × 10 nm2 are performed. The subthreshold characteristics, threshold voltages, and ON-state currents for the three respective transport directions of the [100], [110], and [111] directions are examined. The device characteristics for the [110] and [111] directions are quite similar in every respect, and the [100] direction has the advantage with regard to the subthreshold behavior when the channel length is aggressively scaled down. The on-current magnitudes for the three respective orientations do not differ much, although the on-current in the [100] direction is a little smaller, compared with that in the other two directions when the channel width becomes smaller. An uncoupled mode space approach has been used to determine the contributions from individual heavy and light hole subbands, enabling an insightful analysis of the device characteristics.

An analytical two-dimensional model for silicon MESFETs

Abstract: A model that predicts small-geometry effects in Si MESFETs has been developed. It is based on a two-dimensional (2-D) analytical solution of Poisson's equation in the subthreshold regime that applies to the junction-isolated structure typical of silicon devices. The model is in excellent agreement with numerical simulations from the PISCES 2-D device analysis program. The analytical model provides the physical basis for a subthreshold current model for small-geometry MESFETs. A scaling scheme for MESFETs, derived from the analytical model, that predicts a minimum-acceptable gate length of 0.15 mu m for these devices is proposed. >

First demonstration of strained SiGe nanowires TFETs with ION beyond 700µA/µm

Abstract: We present for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si 1-x Ge x (x=0, 0.2, 0.25) nanowires, Si 0.7 Ge 0.3 Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. We analyse the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices are also investigated, showing a W -3 dependence of ON current (I ON ) per wire. The fabricated devices exhibit higher I ON than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.

Ultrafast Measurement on NBTI

Abstract: We combine customary pulsed I- V setup with a simple linear drain-current correction method to provide a possible standard for NBTI characterization. The method is implemented using standard equipment and yet is able to achieve sub-100-ns delay, the shortest reported to date for a wafer-level setup. Unlike the ramped-voltage method for which synchronization of the gate and drain waveforms is critical, relative delay between the gate and drain signals is not a concern in our case since measurement is made during quasi-steady state. For the present setup, gate and drain signals are shown to ldquostabilizerdquo after ~50 ns (upon switching) for a gate capacitive load of 1.5 pF (equivalent to ~80 devices used in this letter), rendering parallel testing possible using a single gate voltage source. Extension of the method for direct threshold voltage extraction by the constant subthreshold drain current approach is also discussed.

Impact of super-steep-retrograde channel doping profiles on the performance of scaled devices

Abstract: Super-steep retrograded (SSR) channels were compared to uniformly doped (UD) channels as devices are scaled down from 250 nm to the 50 nm technology node, according to the scheme targeted by the National Technology Roadmap for Semiconductors (1997). The comparison was done at the same gate length L/sub gate/ and the same off-state leakage current I/sub off/, where it was found that SSR profiles always have higher threshold voltages, poorer subthreshold swings, higher linear currents, and lower saturation currents than UD profiles. Using a simulation strategy that takes into account the impact of short-channel effects on drive current, it was found that the improved short-channel effect of retrograde profiles is not enough to translate into a higher performance over the UD channels for all technologies. Hence, if the effective gate-dielectric thickness scales linearly with technology, retrograde doping will not be useful from a performance point of view. However, if the scaling of the gate-dielectric is limited to about 2 nm, SSR profiles can give higher drive current than UD channels for the end of the roadmap devices. Thus, the suitability of SSR channels over UD channels depends on the gate-dielectric scaling strategy. Simulations using a self-consistent Schrodinger-Poisson solver were also used to show that the impact of quantum mechanical (QM) effects on the long-channel characteristics of SSR and UD MOSFET's will be similar.