Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

A Short-Channel $I$ – $V$ Model for 2-D MOSFETs

Abstract: This paper presents an analytic $I$ – $V$ model for short-channel MOSFETs made of 2-D semiconductor material. First, a subthreshold current model is formulated based on the solutions to 2-D Poisson’s equation with negligible mobile charge. Next, a velocity saturation model is developed under the framework of a drift and diffusion long-channel model. These two models are then unified into an all region, short-channel $I$ – $V$ model with both drain induced barrier lowering and velocity saturation effects. Ballistic currents, including the intraband tunneling and the above-the-barrier transport, have been examined and compared with the thermionic currents.

Influence of the channel width on the threshold voltage modulation in m.o.s.f.e.t.s

Abstract: The threshold vollage of an m.o.s. field-effect transistor is modulated by the source-to-substrate reverse bias. In the letter, the theory for long- and short-channel transistors is extended to include the influence of the channel width. The result is an analytical expression for the threshold voltage as a function of geometry and bias that agrees well with experimental data.

WSe2/SnSe2 vdW heterojunction Tunnel FET with subthermionic characteristic and MOSFET co-integrated on same WSe2 flake

Abstract: Two-dimensional/two-dimensional (2D/2D) heterojunctions form one of the most versatile technological solutions for building tunneling field effect transistors because of the sharp and potentially clean interfaces resulting from van der Waals assembly. Several evidences of room temperature band-to-band tunneling (BTBT) have been recently reported, but only few tunneling devices have been proven to break the Boltzmann limit of the minimum subthreshold slope, 60 mV per decade at 300 K. Here, we report the fabrication and characterization of a vertical p-type Tunnel FET (TFET) co-integrated on the same flake with a p-type MOSFET in a WSe2/SnSe2 material system platform. Due to the selected beneficial band alignment and to a van der Waals device architecture having an excellent heterostructure 2D–2D interface, the reported tunneling devices have a sub-thermionic point swing, reaching a value of 35 mV per decade, while maintaining excellent ON/OFF current ratio in excess of 105 at VDS = 500 mV. The TFET characteristics are directly compared with the ones of a WSe2 MOSFET realized on the very same flake used in the heterojunction. The tunneling device clearly outperforms the 2D MOSFET in the subthreshold region, crossing its characteristic over several orders of magnitude of the output current and providing better digital and analog figures of merit.

Simultaneous subthreshold and gate-oxide tunneling leakage current analysis in nanometer CMOS design

Abstract: In this paper we develop a fast approach to analyze the total leakage power of a large circuit block, considering both gate leakage, I/sub gate/, and subthreshold leakage, I/sub sub/. The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies. We propose simple and accurate heuristics to quickly estimate the state-dependent total leakage current considering the interaction between I/sub sub/ and I/sub gate/. We apply this method to ISCAS benchmark circuits in a projected 100 nm technology and demonstrate excellent accuracy compared to SPICE simulation with a 20,000X speedup on average.