Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Analytical Delay Model Considering Variability Effects in Subthreshold Domain

Abstract: The demand of ultralow-power circuits has significantly increased in the last few years. Owing to its great potential in energy savings, the use of supply voltage near or below the transistors' threshold voltages has gained particular attention. Designing these kinds of circuits is still a challenge, particularly when latest advanced process technologies are employed. This brief proposes novel analytical delay models for CMOS circuits running in the subthreshold regime. The delay models proposed here take the effects of the process variability and of the transient variation of the transistors' on-current during the switching into account. Owing to this, delays are predicted with accuracy significantly higher than existing accurate delay models. Furthermore, the novel models are also suitable for gates with transistors' stacks.

A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI

Abstract: Gain-cell embedded DRAM (GC-eDRAM) is a possible alternative to traditional static random access memories (SRAM). While GC-eDRAM provides high-density, low-leakage, low-voltage, and inherent2-ported operation, its limited retention time requires periodic, power-hungry refresh cycles. This drawback is further aggravated at scaled technologies, where increased subthreshold leakage currents and decreased in-cell storage capacitances result in faster data integrity deterioration. Therefore, integration of GC-eDRAM within modern systems is often considered to be limited to mature process technologies, where these phenomena are less detrimental. In this paper, we present for the first time a fully functional GC-eDRAM array, implemented and fabricated in a 28-nm process node. The 8-kb array is based on a novel, 2-ported, 4-transistor NMOS-only bitcell with internal feedback to provide efficient operation in the target 28-nm FD-SOI technology. The fabricated memory macro achieves more than 1.6-ms data retention time at 27 °C, which is $30\times $ longer than conventional gain-cell topologies when applied to this technology. The described 4-transistor dual-port nMOS array utilizes over 70% of the total memory macro area, while retaining almost 30% lower cell area than a single-ported 6T SRAM in the same technology.

Ultralow-Power Operation in Subthreshold Regimes Applying Clockless Logic

Abstract: Energy performance requirements are causing designers of next-generation systems to explore approaches to lowest possible power consumption Subthreshold operation is being examined to stretch low-power circuit designs beyond the normal modes of operation, with the potential for large energy savings Some of the challenges to be overcome, like 10-100× performance penalties, are being addressed by research into parallelism However, the uncertainty in timing generated by operating in subthreshold represents a major challenge to overcome In this paper, first, we will introduce some background information on digital logic subthreshold operation, then provide some background on clockless logic design approaches giving a brief overview of some of the characteristics of the different design styles and focusing on NULL convention logic Next, we will examine the application of that clockless logic approach to a military system, reviewing the background of the experiment, factors considered in the comparison, and then summarizing the results of the comparisons Finally, an overview of additional research and development that will be needed to make the technique available to subthreshold designers is presented

Node voltage dependent subthreshold leakage current characteristics of dynamic circuits

Abstract: The subthreshold leakage current characteristics of domino logic circuits is evaluated in this paper. The strong dependence of the subthreshold leakage current on the node voltages is discussed. In a standard low threshold voltage domino logic circuit with stacked pulldown devices, a charged state rather than a discharge state of the dynamic node is preferred for lower leakage current. Alternatively, the subthreshold leakage current of a dual threshold voltage domino logic circuit is significantly reduced provided that the dynamic node is discharged. A dual threshold voltage circuit has degraded noise immunity characteristics as compared to a standard low threshold voltage circuit. Both keeper and output inverter sizing are necessary to compensate for this degradation in noise immunity. An alternative dual threshold voltage domino circuit technique employing a low threshold voltage keeper for enhanced noise immunity is also considered in this paper. Under similar noise immunity conditions as compared to a standard low threshold voltage domino logic circuit, the savings in subthreshold leakage current offered by a dual threshold voltage circuit technique with a high threshold voltage keeper is significantly higher than the savings offered by a dual threshold voltage circuit technique with a low threshold voltage keeper.