Topic
Subthreshold conduction
About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.
Papers published on a yearly basis
Papers
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TL;DR: In this article, the drain current of partially-depleted (PD) SOI MOSFETs was examined as a function of drain bias, gate pulses of varying magnitude (V/sub GS/), pulse duration, and pulse frequency.
Abstract: The behavior of transients in the drain current of partially-depleted (PD) SOI MOSFET's down to L/sub eff/=0.2 /spl mu/m is examined as a function of drain bias, gate pulses of varying magnitude (V/sub GS/), pulse duration, and pulse frequency. At fixed V/sub DS/, the gate is pulsed to values ranging from 0.1 V above V/sub T/ to V/sub GS/=V/sub DS/. A slow transient is seen when the drain is biased at a V/sub DS/ where the current kink is observable. This slow transient can be on the order of microseconds depending on the relative magnitude of the impact ionization rate. For short times after the pulse edge or for very short pulses at low frequencies, it is shown that the subthreshold drain current value can be very different from the corresponding DC, and that the kink characteristic of PD MOSFET's disappears. However, the kink values can be approached when the pulse frequency and/or duration applied to the gate is increased, due to the latent charge maintained in the floating body at higher frequencies. No transient current effects were observed in fully-depleted SOI MOSFET's. >
42 citations
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TL;DR: In this paper, the authors investigated hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs and showed that trap-assisted drain leakage may become a dominant drain leakage mechanism as supply voltage is reduced.
Abstract: The mechanisms and characteristics of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero V/sub gs/ such as drain-to source subthreshold leakage, band-to-band tunneling current, and interface trap-induced leakage are taken into account. The trap-assisted drain leakage mechanisms include charge sequential tunneling current, thermionic-field emission current, and Shockley-Read-Hall generation current. The dependence of drain leakage current on supply voltage, temperature, and oxide thickness is characterized. Our result shows that the trap-assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, a strong oxide thickness dependence of drain leakage degradation is observed. In ultra-thin gate oxide (30 /spl Aring/) n-MOSFETs, drain leakage current degradation is attributed mostly to interface trap creation, while in thicker oxide (53 /spl Aring/) devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by an accelerated degradation rate in the second stage caused by oxide charge creation.
42 citations
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13 Jun 2005TL;DR: A logic synthesis approach based on Shannon expansion is proposed that dynamically applies supply gating to idle parts of general logic circuits even when they are performing useful computation.
Abstract: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode. We present a novel low-cost design methodology with associated synthesis flow for reducing both switching and active leakage power using dynamic supply gating. A logic synthesis approach based on Shannon expansion is proposed that dynamically applies supply gating to idle parts of general logic circuits even when they are performing useful computation. Experimental results on a set of MCNC benchmark circuits in a predictive 70nm process exhibits improvements of 15% to 88% in total active power compared to the results obtained by a conventional optimization flow.
42 citations
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27 Sep 1995
TL;DR: In this article, a wireless infrared pulse-transmitting system for communication with electronic components is described, where the receiver for such a system has a radically reduced current and power values, which permit a battery-powered receiver to remain on while awaiting transmitter signals.
Abstract: A wireless infrared pulse-transmitting system for communication with electronic components. The receiver (30) for such a system has a radically reduced current (and power) values, which permit a battery-powered receiver to remain on while awaiting transmitter signals. Use of several mosfet transistors operating in the subthreshold region minimizes power. Bandwidth requirements are met, in spite of the low power operation. In order to eliminate amplifier (40) saturation, with the accompanying problem of recovery time which slows the transmission process, clamping circuitry (46) is used to cause instantaneous shunting of the signals when a predetermined signal level is reached.
42 citations
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TL;DR: In this article, a new alternative technique is proposed to extract the threshold voltage from the subthreshold-to-strong inversion transition region of MOSFETs using an auxiliary operator that involves integration of the drain current as a function of gate voltage.
Abstract: A new alternative technique is proposed to extract the threshold voltage from the subthreshold-to-strong inversion transition region of MOSFETs. It uses an auxiliary operator that involves integration of the drain current as a function of gate voltage. Tests show that the procedure produces results comparable to conventional methods.
42 citations