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Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.


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Journal ArticleDOI
TL;DR: A strong silicon physical unclonable function (PUF) resistant to machine learning (ML) attacks is presented, which shows negligible loss in PUF unpredictability and $\sim 100\times $ higher resilience than the 65-bit arbiter PUF, 3-XORPUF, and 3- XOR lightweight (LW) PUF.
Abstract: This paper presents a strong silicon physical unclonable function (PUF) resistant to machine learning (ML) attacks. The PUF, termed the subthreshold current array PUF (SCA-PUF), consists of a pair of two-dimensional transistor arrays and a low-offset comparator. The proposed 65-bit SCA-PUF is fabricated in a 130nm process and allows 265 challenge-response pairs (CRPs). It consumes 68nW and 11pJ/bit while exhibiting high uniqueness, uniformity, and randomness. It achieves bit error rate (BER) of 5.8% for the temperature range of −20 to 80°C and supply voltage variation of ±10%. The calibration-based CRP selection method improves BER to 0.4% with a 42% loss of CRPs. When subjected to ML attacks, the prediction error stays over 40% on 104 training points, which shows negligible loss in PUF unpredictability and $\sim 100\times $ higher resilience than the 65-bit arbiter PUF, 3-XOR PUF, and 3-XOR lightweight (LW) PUF.

41 citations

Proceedings ArticleDOI
27 May 2007
TL;DR: New low-leakage circuit techniques based on multi-threshold-voltage and multi-oxide-thickness standard single-gate and emerging double-gate MOSFET/FinFET technologies are presented in this paper.
Abstract: In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circuit techniques based on multi-threshold-voltage (multi-Vt) and multi-oxide-thickness (multi-tox) standard single-gate and emerging double-gate MOSFET/FinFET technologies are presented in this paper. The leakage savings achieved with the techniques are characterized for a diverse set of logic and memory circuits that are widely used in systems-on-chips. The speed, active power, noise immunity, and area tradeoffs with the leakage reduction schemes are also evaluated.

41 citations

Journal ArticleDOI
TL;DR: A qualified performance of the proposed SRAM cell is demonstrated in terms of power dissipation, power–delay product, write margin, read access time and sensitivity to process, voltage and temperature variations as compared to the other most efficient low-voltage SRAM cells previously presented in the literature.
Abstract: This paper presents a new nine-transistor (9T) SRAM cell operating in the subthreshold region. In the proposed 9T SRAM cell, a suitable read operation is provided by suppressing the drain-induced barrier lowering effect and controlling the body---source voltage dynamically. Proper usage of low-threshold voltage (L-$$V_{\mathrm{t}}$$Vt) transistors in the proposed design helps to reduce the read access time and enhance the reliability in the subthreshold region. In the proposed cell, a common bit-line is used in the read and write operations. This design leads to a larger write margin without using extra circuits. The simulation results at 90 nm CMOS technology demonstrate a qualified performance of the proposed SRAM cell in terms of power dissipation, power---delay product, write margin, read access time and sensitivity to process, voltage and temperature variations as compared to the other most efficient low-voltage SRAM cells previously presented in the literature.

41 citations

Journal ArticleDOI
Liang Wen1, Xu Cheng1, Shudong Tian1, Wen Haibo1, Xiaoyang Zeng1 
TL;DR: A new subthreshold level shifter capable of converting an input signal from a deep subth threshold voltage to an above-threshold voltage is presented in this brief and can realize a robust voltage conversion from 0.1 to 1.2 V with limited static power and energy consumption.
Abstract: A new subthreshold level shifter capable of converting an input signal from a deep subthreshold voltage to an above-threshold voltage is presented in this brief. The circuit utilizes a self-controlled current limiter to implement level shifting by detecting output error. Owing to to this technique, measured results from a 65-nm test chip demonstrate that it can realize a robust voltage conversion from 0.1 to 1.2 V with limited static power and energy consumption. At the target voltage of 0.2 V, the level converter could operate reliably at a maximum input frequency of 254 kHz.

41 citations

Journal ArticleDOI
TL;DR: In this paper, the effective thickness of the amorphous chalcogenide part within the active element of a phase-change memory cell was estimated through electrical measurements, and the results serve to further validate the trap-limited conduction model, as well as the series phase distribution hypothesis in the active layer of the phase change memory cell.
Abstract: The effective thickness of the amorphous chalcogenide part within the active element of a phase-change memory cell is estimated through electrical measurements. Current–voltage characteristics obtained at various intermediate cell states are fitted with the trap-limited subthreshold transport model of [9] and the amorphous part thickness is then extracted. Several cell electrical measures, such as the resistance and the threshold voltage, are shown to closely relate to the estimated parameter. The results serve to further validate the trap-limited conduction model, as well as the series phase distribution hypothesis in the active layer of a phase-change memory cell.

41 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023153
2022349
2021172
2020196
2019242
2018272