Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

A Universal Core Model for Multiple-Gate Field-Effect Transistors. Part II: Drain Current Model

Abstract: A universal drain current model for multiple-gate field-effect transistors (FETs) (Mug-FETs) is proposed. In Part I, a universal charge model was derived using the arbitrary potential method. Using this charge model, Pao-Sah's integral is analytically carried out by approximating its integrand. The model describes both the subthreshold inversion for undoped FETs and the effects of finite doping density in the channel. With an explicit and continuous expression, the proposed drain current model covers all regions of device operation: subthreshold, linear, and saturation. The accuracy from the proposed model is comparable with that from well-known previous models for double-gate (DG) and cylindrical gate-all-around (Cy-GAA) FETs with an undoped channel. In addition, the model shows good agreement with 2-D and 3-D numerical simulations for doped-channel multiple-gate structures such as single-gate, DG, triple-gate, rectangular gate-all-around, and Cy-GAA FETs. The proposed model is well suited to be a core model for Mug-FETs due to its good computational efficiency and high accuracy; hence, it is useful for compact modeling.

SLC: Split-control Level Converter for dense and stable wide-range voltage conversion

Abstract: Ultra-low voltage design makes signal level conversion a critical component in modern low power designs. This paper proposes a static level converter operating in the subthreshold regime, called SLC (Split-control Level Converter). Using a novel circuit structure, SLC effectively eliminates the high leakage and short circuit currents in previous approaches. Designed for 300mV to 2.5V conversion and fabricated in 130nm CMOS, measured results show 2.3×, 9.9×, and 5.9× improvements over conventional DCVS structures in delay, static power, and energy per transition, respectively. Even with the smallest area among wide-range level converters, it also has 5.2× smaller standard deviation in delay and only 5.6% change in FO4 delay with 10% V DDL drop, demonstrating robustness.

Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits

Abstract: This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing ( $S.S.$ ) and comparable trap-induced $V_{T}$ shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage $(V_{\rm dd})$ , the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way nand, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause $\sim$ 24%–27% and $\sim$ 13%–15% variations in leakage and delay at $V_{ \rm dd} = \hbox{0.4}\ \hbox{V}$ , respectively, for the logic circuits evaluated.

Analysis of subthreshold carrier transport for ultimate DGMOSFET

Abstract: A novel transport model for the subthreshold mode of double-gate MOSFETs (DGMOSFETs) is proposed in this paper. The model enables the analysis of short-channel effects (SCEs) such as the subthreshold swing (SS), the threshold-voltage rolloff, and the drain-induced barrier lowering. The proposed model includes the effects of thermionic emission and the quantum tunneling of carriers through the source-drain barrier. An approximative solution of the two-dimensional Poisson equation is used for the distribution of the electric potential, and the Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The model is verified by comparing the SS with numerical simulations. The new model is used to investigate the subthreshold characteristics of a DGMOSFET having the gate length in the nanometer range with an ultrathin gate oxide and channel thickness. The SCEs degrade the subthreshold characteristics of DGMOSFETs when the gate length is reduced below 10 nm, and any design in the sub-10-nm-regime should include the effects of quantum tunneling.