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Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.


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Patent
23 Jan 1998
TL;DR: In this paper, a master cell is configured to regulate the bias voltage precisely over a wide range of load currents from the slave cells, thus eliminating the need for a current boosting voltage follower between the master cell and each slave cell.
Abstract: Methods and circuits for biasing a transconducting cell to operate in a subthreshold state so as to have a desired high transconductance, and systems including a master cell for generating a regulated bias voltage and one or more transconducting slave cells biased in subthreshold by the bias voltage. An example of such system is an inverting voltage amplifier (offering low power consumption, low noise, good stability, and high gain). The bias voltage is generated to be independent of process and environmental variations by servoing an unregulated supply voltage, and preferably has lower magnitude relative to ground than the supply voltage. Preferably, the master cell includes transistors in which a constant current density is maintained, and this current density is replicated in each slave cell biased by the master cell. Preferably, the master cell is configured to regulate the bias voltage precisely over a wide range of load currents from the slave cells, thus eliminating the need for a current boosting voltage follower between the master cell and each slave cell. The slave cell can comprise multiple transconducting stages (each biased in subthreshold), an integrator having multiple inverter stages (and at least one feedback stage providing displacement current to one of the stages), cascoded transistor pairs, or an NMOS transistor and PMOS transistor biased in subthreshold with gate potentials offset by different amounts above and below an input voltage.

40 citations

Proceedings ArticleDOI
Sakata1, Horiguchi1, Itoh1
19 May 1993
TL;DR: In this paper, innovative circuits featuring a hierarchical power-line scheme and a switched-power-supply CMOS inverter with a level holder are proposed that can drastically reduce even the active current of a 16 Gbit DRAM by one tenth.
Abstract: Subthreshold-current reduction, especially at room-temperature operation, is one of the key design issues in the gigabit era. Despite its importance, however, a scheme for it has not been proposed. In this paper, innovative circuits featuring a hierarchical power-line scheme and a switched-power-supply CMOS inverter with a level holder are proposed. They can drastically reduce even the active current of a 16 Gbit DRAM by one tenth, from 1.2A to 116mA.

39 citations

Journal ArticleDOI
TL;DR: In this paper, the influence of drain and source contacts on device parameters including the mobility, the threshold voltage, and the sub-threshold slope was discussed in detail, and it was shown that contact effects limit the performance of the transistors.
Abstract: Microcrystalline silicon thin-film transistors were prepared by plasma-enhanced chemical vapor deposition at substrate temperatures below 200°C. The transistors exhibit electron mobilities of 38cm2∕Vs, threshold voltages in the range of 2V, and subthreshold slopes of 0.3V∕decade. Despite the realization of transistors with high carrier mobility, contact effects limit the performance of the transistors. The influence of the drain and source contacts on device parameters including the mobility, the threshold voltage, and the subthreshold slope will be discussed in detail.

39 citations

Journal ArticleDOI
TL;DR: An automatic V"T-extractor circuit is proposed which allows the direct determination of the threshold voltage with minimum influence of second-order effects and three procedures based on dc current measurements are proposed.

39 citations

Journal ArticleDOI
TL;DR: An ultra-low power and wide bandwidth operational transconductance amplifier (OTA) that provides the advantages of rail-to-rail input and output swing, while presenting lower power consumption and higher DC gain than conventional FC with enhanced current recycling technique is presented.

39 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023153
2022349
2021172
2020196
2019242
2018272