Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Determination of the subthreshold state contribution in 13C(alpha,n)16O, the main neutron-source reaction for the s process.

Abstract: The reaction rate of the stellar reaction 1 3 C(α, n) 1 6 O, which is currently considered to be the main neutron source for the slow (s) process at low energies, has been rederived using the direct α-transfer reaction 1 3 C( 6 Li, d) 1 7 O leading to the subthreshold state at 6.356 MeV in 1 7 O. The contribution of the subthreshold state is found to be much smaller than the currently accepted predictions for the main neutron source of the s process, indicating less of a role of this reaction as the neutron source for the s-process scenario in low-mass stars at the asymptotic giant branch.

MOSFET scaling limits determined by subthreshold conduction

Abstract: The formulation and solution of the equations governing transistor subthreshold behavior in explicit analytical form provide quantitative predictions for minimum feature length as well as immediate information on the relative importance of all major transistor fabrication parameters. Such a formulation and a solution for subthreshold conduction are presented. The importance of gate oxide thickness, channel impurity concentration, source-drain junction depth, and applied potentials are examined. The results suggest that successful advanced process development programs must devise methods for ultrashallow ( >

Nanopower Subthreshold MCML in Submicrometer CMOS Technology

Abstract: This paper presents subthreshold MOS current-mode logic (MCML) circuits implemented in a commercial 0.25-mum CMOS technology. We propose the adoption of bulk-drain-connected pMOS transistors as loads for subthreshold MCML gates. The b-d connection extends the linear operating range of the load, thus increasing the output logic swing of the subthreshold MCML gate. Theoretical and measured results are presented for an MCML inverter and a ten-stage ring oscillator operating at supply voltages below the threshold-voltage value, with power consumption on the order of nanowatts. At a 300-mV supply, the oscillator works at a frequency of 638 Hz with a total power consumption of 345 pW.

A transregional model for near-threshold circuits with application to minimum-energy operation

Abstract: The most energy-efficient operating point for CMOS circuits is near the threshold voltage. Conventional models are difficult to use in this region because they are piecewise and/or discontinuous around threshold. This paper proposes a simple new model for I on that is valid in the near-threshold region. Based on the ON-current, a propagation delay model is derived. The model is applied to determine the minimum energy point for inverter chains. The transregional model matches simulated data within 15 mV, while the conventional exponential subthreshold model underestimates the supply voltage by up to 80 mV.

Low vt antifuse device

Abstract: A one time programmable memory cell having an anti-fuse device with a low threshold voltage independent of core circuit process manufacturing technology is presented. A two transistor memory cell having a pass transistor and an anti-fuse device, or a single transistor memory cell having a dual thickness gate oxide, are formed in a high voltage well that is formed for high voltage transistors. The threshold voltage of the anti-fuse device differs from the threshold voltages of any transistor in the core circuits of the memory device, but has a gate oxide thickness that is the same as a transistor in the core circuits. The pass transistor has a threshold voltage that differs from the threshold voltages of any transistor in the core circuits, and has a gate oxide thickness that differs from any transistor in the core circuits. The threshold voltage of the anti-fuse device is lowered by omitting some or all of the threshold adjustment implants that is used for high voltage transistors fabricated in the I/O circuits.