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Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.


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Proceedings ArticleDOI
10 Jun 2003
TL;DR: In this article, the Tri-Gate body dimensions are compared to single-gate or double-gate devices, and the corner plays a fundamental role in determining the device I-V characteristics.
Abstract: Tri-Gate fully-depleted CMOS transistors have been fabricated with various body dimensions. These experimental results and 3-D simulations are used to explore the design space for full depletion, as well as layout issues for the Tri-Gate architecture, down to 30 nm gate lengths. It is found not only that the Tri-Gate body dimensions are flexible and relaxed compared to single-gate or double-gate devices, but that the corner plays a fundamental role in determining the device I-V characteristics. The corner device not only turns on at lower voltages due to the proximity of two adjacent gates, but the DIBL of this part of the device is much smaller than the rest of the transistor. The shape of the subthreshold I-V characteristics and the degree of DIBL control, as well as the early device turn-on are also greatly affected by the degree of body corner rounding. Examination of layout issues shows that the fin-doubling approach from using a spacer printing technique results in an increase in drive current of 1.2 times that of a planar device for a given width, though the shape of the allowed Tri-Gate fins has certain restrictions.

256 citations

Journal ArticleDOI
TL;DR: Flexible transistors were fabricated by sputter deposition of zinc tin oxide (ZTO) onto plasma-enhanced chemical vapor deposition gate dielectrics formed on flexible polyimide substrates with a blanket aluminum gate electrode, and they exhibited high on-currents of 1mA, on/off ratios of 106, subthreshold voltage slopes of 1.6V/decade, turn-on voltages of −17V, and mobilities of 14cm2V−1s−1.
Abstract: Flexible transistors were fabricated by sputter deposition of zinc tin oxide (ZTO) onto plasma-enhanced chemical vapor deposition gate dielectrics formed on flexible polyimide substrates with a blanket aluminum gate electrode. The flexible transistors exhibited high on-currents of 1mA, on/off ratios of 106, subthreshold voltage slopes of 1.6V/decade, turn-on voltages of −17V, and mobilities of 14cm2V−1s−1. Capacitance measurements indicate that the threshold voltage and subthreshold slope are primarily influenced by residual doping in the ZTO rather than by defects at the semiconductor/dielectric interface, and are useful for assessing contact resistance.

256 citations

Journal ArticleDOI
TL;DR: A voltage reference circuit operating with all transistors biased in weak inversion, providing a mean reference voltage of 257.5 mV, has been fabricated in 0.18 m CMOS technology with accurate subthreshold design.
Abstract: A voltage reference circuit operating with all transistors biased in weak inversion, providing a mean reference voltage of 257.5 mV, has been fabricated in 0.18 m CMOS technology. The reference voltage can be approximated by the difference of transistor threshold voltages at room temperature. Accurate subthreshold design allows the circuit to work at room temperature with supply voltages down to 0.45 V and an average current consumption of 5.8 nA. Measurements performed over a set of 40 samples showed an average temperature coefficient of 165 ppm/ C with a standard deviation of 100 ppm/ C, in a temperature range from 0 to 125°C. The mean line sensitivity is ≈0.44%/V, for supply voltages ranging from 0.45 to 1.8 V. The power supply rejection ratio measured at 30 Hz and simulated at 10 MHz is lower than -40 dB and -12 dB, respectively. The active area of the circuit is ≈0.043mm2.

254 citations

Journal ArticleDOI
TL;DR: In this paper, a 2D analytical solution of electrostatic potential is derived for undoped (or lightly doped) double-gate (DG) MOSFETs in the sub-threshold region by solving Poissons equation in a 2-D boundary value problem.
Abstract: A two-dimensional (2-D) analytical solution of electrostatic potential is derived for undoped (or lightly doped) double-gate (DG) MOSFETs in the subthreshold region by solving Poissons equation in a 2-D boundary value problem. It is shown that the subthreshold current, short-channel threshold voltage rolloff and subthreshold slope predicted by the analytical solution are in close agreement with 2-D numerical simulation results for both symmetric and asymmetric DG MOSFETs without the need of any fitting parameters. The analytical model not only provides useful physics insight into short-channel effects, but also serves as basis for compact modeling of DG MOSFETs.

251 citations

Journal ArticleDOI
TL;DR: It is shown that a single arsenic dopant atom dramatically affects the off-state room-temperature behaviour of a short-channel field-effect transistor fabricated with standard microelectronics processes, and suggests a path to incorporating quantum functionalities into silicon CMOS devices through manipulation of single donor orbitals.
Abstract: A single dopant atom can dominate the subthreshold behaviour of a field-effect transistor, and this effect is enhanced if the atom is located near a dielectric.

250 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023153
2022349
2021172
2020196
2019242
2018272