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Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.


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Journal ArticleDOI
TL;DR: This work presents an atomic threshold-switching field-effect transistor constructed by integrating a metal filamentary threshold switch with a two-dimensional MoS2 channel, and obtains abrupt steepness in the turn-on characteristics and 4.5 mV decade−1 subthreshold swing (over five decades).
Abstract: Power dissipation is a fundamental issue for future chip-based electronics. As promising channel materials, two-dimensional semiconductors show excellent capabilities of scaling dimensions and reducing off-state currents. However, field-effect transistors based on two-dimensional materials are still confronted with the fundamental thermionic limitation of the subthreshold swing of 60 mV decade−1 at room temperature. Here, we present an atomic threshold-switching field-effect transistor constructed by integrating a metal filamentary threshold switch with a two-dimensional MoS2 channel, and obtain abrupt steepness in the turn-on characteristics and 4.5 mV decade−1 subthreshold swing (over five decades). This is achieved by using the negative differential resistance effect from the threshold switch to induce an internal voltage amplification across the MoS2 channel. Notably, in such devices, the simultaneous achievement of efficient electrostatics, very small sub-thermionic subthreshold swings, and ultralow leakage currents, would be highly desirable for next-generation energy-efficient integrated circuits and ultralow-power applications. Here, the authors demonstrate an atomic threshold-switching field-effect transistor constructed by integrating a metal filamentary switch with a two-dimensional MoS2 channel, and obtain abrupt steepness in the turn-on characteristics and 4.5 mV/dec subthreshold swing over five decades.

37 citations

Journal ArticleDOI
TL;DR: In this paper, N2O plasma treatment on active layer was expected to avert defects generation during SiO2 deposition process, which not only suppresses sub-reshold current stretch-out phenomenon but also significantly improves the bias stress stability in a-IGZO TFTs at high temperature.
Abstract: An abnormal subthreshold leakage current is observed at high temperature, which causes a notable stretch-out phenomenon in amorphous InGaZnO thin film transistors (a-IGZO TFTs). This is due to trap-induced thermal-generated holes accumulating at the source region, which leads to barrier lowering on the source side and causes an apparent subthreshold leakage current. In order to obtain superior thermal stability performance of a-IGZO TFTs, conducting N2O plasma treatment on active layer was expected to avert defects generation during SiO2 deposition process. Reducing defects generation not only suppresses subthreshold current stretch-out phenomenon but also significantly improves the bias stress stability in a-IGZO TFTs at high temperature.

37 citations

Journal ArticleDOI
TL;DR: This paper presents a new average-8T write/read decoupled (A8T-WRD) SRAM architecture for low-power sub/near-threshold SRAM in power-constraint applications such as biomedical implants and autonomous sensor nodes.
Abstract: This paper presents a new average-8T write/read decoupled (A8T-WRD) SRAM architecture for low-power sub/near-threshold SRAM in power-constraint applications such as biomedical implants and autonomous sensor nodes. The proposed architecture consists of several novel concepts in dealing with issues in sub/near-threshold SRAM including: 1) the differential and data-independent-leakage read port that facilitates robust and faster read operation and alleviates issues in the half-selected cell (pseudo-write) while reducing the area compared to the conventional 8T cell and 2) the various configurations from 14T for a baseline cell to 6.5T for an area-efficient 16-bit cell. These configurations reduce the overall bitcell area and enable low operating voltage. Two memory blocks based on the proposed architecture at the size of 16 and 64 kb, respectively, are fabricated in 0.13-μm CMOS process. The 64 kb prototype has an active area of 0.512 mm2 which is 16% less than that of the conventional 8T-cell-based design. The chip is fully functional for the read operation with 260 mV at 245 kHz and 270 mV for the write operation at 1 MHz. It can hold data down to 170 mV where the standby power consumption is only 884 nW.

37 citations

Journal ArticleDOI
Minsuk Kim1, Yoonjoong Kim1, Doohyeok Lim1, Sola Woo1, Kyoungah Cho1, Sangsig Kim 
TL;DR: The authors' proposed feedback field-effect transistors exhibit subthreshold swings of less than 0.1 mV dec-1, an on/off current ratio of approximately 1011, and an on-current of approximately 10-4 A at room temperature, demonstrating that the switching characteristics are superior to those of other silicon-based devices.
Abstract: In this study, we propose newly designed feedback field-effect transistors that utilize the positive feedback of charge carriers in single-gated silicon channels to achieve steep switching behaviors. The band diagram, I–V characteristics, subthreshold swing, and on/off current ratio are analyzed using a commercial device simulator. Our proposed feedback field-effect transistors exhibit subthreshold swings of less than 0.1 mV dec−1, an on/off current ratio of approximately 1011, and an on-current of approximately 10−4 A at room temperature, demonstrating that the switching characteristics are superior to those of other silicon-based devices. In addition, the device parameters that affect the device performance, hysteresis characteristics, and temperature-dependent device characteristics are discussed in detail.

37 citations

Proceedings ArticleDOI
12 Nov 2012
TL;DR: To minimize leakage power during standby, a single custom-designed standard-cell (D-latch with 3-state output buffer) addressing all major leakage contributors of SCMs is seamlessly integrated into the fully automated SCM compilation flow.
Abstract: Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-V T ) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforward approach to realize robust sub-V T storage arrays and fill the gap of missing sub-V T memory compilers. This paper presents an ultra-low-leakage 4kb SCM manufactured in 65nm CMOS technology. To minimize leakage power during standby, a single custom-designed standard-cell (D-latch with 3-state output buffer) addressing all major leakage contributors of SCMs is seamlessly integrated into the fully automated SCM compilation flow. Silicon measurements of a 4kb SCM indicate a leakage power of 500fW per stored bit (at a data-retention voltage of 220 mV) and a total energy of 14 fJ per accessed bit (at energy-minimum voltage of 500mV), corresponding to the lowest values in 65nm CMOS reported to date.

37 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023153
2022349
2021172
2020196
2019242
2018272