Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Nanomechanical silicon resonators with intrinsic tunable gain and sub-nW power consumption.

Abstract: Nanoelectromechanical systems (NEMS) as integrated components for ultrasensitive sensing, time keeping, or radio frequency applications have driven the search for scalable nanomechanical transduction on-chip. Here, we present a hybrid silicon-on-Insulator platform for building NEM oscillators in which fin field effect transistors (FinFETs) are integrated into nanomechanical silicon resonators. We demonstrate transistor amplification and signal mixing, coupled with mechanical motion at very high frequencies (25-80 MHz). By operating the transistor in the subthreshold region, the power consumption of resonators can be reduced to record-low nW levels, opening the way for the parallel operation of hundreds of thousands of NEM oscillators. The electromechanical charge modulation due to the field effect in a resonant transistor body constitutes a scalable nanomechanical motion detection all-on-chip and at room temperature. The new class of tunable NEMS represents a major step toward their integration in resonator arrays for applications in sensing and signal processing.

Sub-1-V swing bus architecture for future low-power ULSIs

Abstract: Reducing the operating voltage is one of the most efficient ways to reduce the power dissipation of deep submicron ULSIs. A new bus architecture that reduces the operating power by using a bus signal swing of less than 1 V is proposed. This enables reduction of the bus swing to 1/3 that of the conventional architecture while maintaining a high speed and a low standby current. This architecture provides an efficient way to relieve the constraint of subthreshold leakage on V/sub CC/ scaling and to reduce the operating power of deep submicron ULSIs. Circuit configuration and performance are presented, together with experimental results. >

Analog CMOS Building Blocks for Custom and Semicustom Applications

Abstract: Standard analog building blocks developed for use in custom and semicustom LSI and VLSI designs are described. The analog blocks are built using a digital CMOS process modified to include high-value resistors and voltage independent capacitors. Designs for operational amplifiers, programmable voltage sources, comparators, band gap voltage references, unit resistors, capacitors, and n-p-n devices are discussed. Performance characteristics including unity-gain bandwidth, output drive, output impedance, and common mode range are reviewed. MOS noise data subthreshold operation, and device matching are analyzed. Layout guidelines are proposed as well as applications and limitations of the analog building blocks.

Novel method for silicon quantum wire transistor fabrication

Abstract: Local stress-limited oxidation was used to fabricate silicon quantum wire transistors with a channel diameter of 5 nm. The oxidation of source and drain regions was prevented with a silicon nitride diffusion barrier. A novel wraparound gate was used to improve the gate control of the potential in the channel. The electrical properties of these devices were investigated at room temperature. Ideal subthreshold behavior, with the subthreshold swing equal to 60.3 mV/dec, was observed.

Enhanced GaAs MESFET CAD model for a wide range of temperatures

Abstract: We describe a new and enhanced GaAs MESFET model suitable for implementation in computer aided design (CAD) software packages such as, for example, SPICE. The model accurately reproduces both above-threshold and subthreshold characteristics of GaAs MESFET's in a wide temperature range, from 77 K to 350/spl deg/C. The current-voltage characteristics are described by a single continuous, analytical expression for all regimes of operation. The physics-based model includes effects such as velocity saturation in the channel, drain induced barrier lowering, finite output conductance in saturation, bias dependent series source and drain resistances, effects of bulk charge, bias dependent average low-field mobility, frequency dependent output conductance, backgating and sidegating, and temperature dependent model parameters. The output resistance and the transconductance are also accurately reproduced, making the model suitable for analog CAD. >