scispace - formally typeset
Search or ask a question
Topic

Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.


Papers
More filters
Journal ArticleDOI
TL;DR: In this article, a compact analytical model is presented for device electrostatics of nanoscale Cylindrical Gate (CylG) Gate-All-Around (GAA) MOSFET, using isomorphic polynomial function for potential distribution.
Abstract: A compact analytical model is presented for device electrostatics of nanoscale Cylindrical Gate (CylG) Gate-All-Around (GAA) MOSFET, using isomorphic polynomial function for potential distribution. The model is based on solutions of 3D Laplace and Poisson’s equations for subthreshold and strong inversion region respectively. In this paper, the short-channel effects are precisely accounted for by introducing z dependent characteristic length and the developed electrostatics is tested against analysis of crossover point for device under test. Further, the modeled subthreshold slope for lightly doped CylG GAA MOSFET has been improved by introducing z dependent characteristic length and the position of minimum center potential in the channel is obtained by virtual cathode position. A new model is proposed for threshold voltage, based on shifting of inversion charge from center line to silicon insulator interface.

36 citations

Journal ArticleDOI
TL;DR: In this article, a simulation model was proposed to explain two-dimensional field effect operation of undoped poly-Si thin-film transistors (TFTs) under small drain voltages.
Abstract: We propose a simulation model to explain two‐dimensional field‐effect operation of undoped poly‐Si thin‐film transistors (TFTs) under small drain voltages. Our model includes both thermionic‐emission and drift‐diffusion conduction processes. We calculated grain‐boundary potential barriers, channel currents, and various device parameters depending on grain size and defect density. In order to validate our model, we compared calculated currents with experimental data for two types of poly‐Si TFTs. We could obtain good current fits simultaneously in both subthreshold and linear regions by adopting proper densities of states in the poly‐Si channels. We could also explain well the temperature‐dependent current changes and the current activation energy versus the gate voltage. Finally, we succeeded in modeling the drain current under small drain voltages by using the combined transport process in the two‐dimensional grain‐boundary structure.

36 citations

Proceedings ArticleDOI
13 Sep 1998
TL;DR: In this paper, a transregional model for conventional surface channel inversion MOSFETs with continuous and smooth transitions at regional boundaries is introduced, which describes all regions of operation, namely, subthreshold, linear, and saturation while including the effects of carrier velocity saturation, vertical and lateral high field mobility degradation, and threshold voltage roll-off.
Abstract: A new compact transregional model for conventional surface channel inversion MOSFETs with continuous and smooth transitions at regional boundaries is introduced. The model, verified against MEDICI and HSPICE, describes all regions of operation, namely, subthreshold, linear, and saturation while including the effects of 1) carrier velocity saturation, 2) vertical and lateral high field mobility degradation, and 3) threshold voltage roll-off, all prominent characteristics of sub-micron devices. The key contribution of this model is the physical insight into the on/off current trade-off that ensues with voltage scaling and will be vital to future low power design. Utilizing the model for a complete power-delay analysis of CMOS circuit designs, analytical expressions are derived for: 1) propagation delay, 2) short circuit power (P/sub SC/), and 3) static power (P/sub Static/). Results from the total power (P/sub Total/) consumption analysis indicate that P/sub SC/ and P/sub Static/ may constitute over 1/3 of P/sub Total/ in future low power/high performance CMOS GSI.

36 citations

Journal ArticleDOI
TL;DR: This study clearly defined and calculated neural energy supply and consumption based on the Hodgkin-Huxley model during firing action potentials and subthreshold activities using ion-counting and power-integral model and found that, under the two circumstances, power synchronization of ion channels and energy utilization ratio have significant differences.
Abstract: Electrical activity is the foundation of the neural system. Coding theories that describe neural electrical activity by the roles of action potential timing or frequency have been thoroughly studied. However, an alternative method to study coding questions is the energy method, which is more global and economical. In this study, we clearly defined and calculated neural energy supply and consumption based on the Hodgkin-Huxley model, during firing action potentials and subthreshold activities using ion-counting and power-integral model. Furthermore, we analyzed energy properties of each ion channel and found that, under the two circumstances, power synchronization of ion channels and energy utilization ratio have significant differences. This is particularly true of the energy utilization ratio, which can rise to above 100% during subthreshold activity, revealing an overdraft property of energy use. These findings demonstrate the distinct status of the energy properties during neuronal firings and subthreshold activities. Meanwhile, after introducing a synapse energy model, this research can be generalized to energy calculation of a neural network. This is potentially important for understanding the relationship between dynamical network activities and cognitive behaviors.

36 citations

Journal ArticleDOI
TL;DR: In this article, the authors proposed the broken-gap tunnel MOSFET (BG-TMOS), which can achieve constant sub-60mV/decade inverse subthreshold slopes at room temperature.
Abstract: We propose a novel low-power transistor device, called the broken-gap tunnel MOSFET (BG-TMOS), which is capable of achieving constant sub-60-mV/decade inverse subthreshold slopes S at room temperature. Structurally, the device resembles an ungated broken-gap heterostructure Esaki region in series with a conventional MOSFET. The gate voltage independence of the energy spacing between the conduction and valence bands at the heterojunction is the key to producing a constant S <; 60 mV/decade, which can be tuned by properly engineering the material composition at this interface. In contrast to the tunneling field-effect transistor, the tunnel junction in the BG-TMOS is independent of the electrostatics in the channel region, enabling the use of 2-D architectures for improved current drive without degradation of S -attractive features from a circuit design perspective. Simulations show that the BG-TMOS can exceed MOSFET performance at low supply voltages.

36 citations


Network Information
Related Topics (5)
CMOS
81.3K papers, 1.1M citations
78% related
Transistor
138K papers, 1.4M citations
77% related
Integrated circuit
82.7K papers, 1M citations
75% related
Amplifier
163.9K papers, 1.3M citations
74% related
Field-effect transistor
56.7K papers, 1M citations
73% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023153
2022349
2021172
2020196
2019242
2018272