Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Shielded channel double-gate MOSFET: a novel device for reliable nanoscale CMOS applications

Abstract: In this paper, the unique features exhibited by a novel double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) in which the front gate consists of two side gates to 1) electrically shield the channel region from any drain voltage variation and 2) act as an extremely shallow virtual extension to the source/drain are presented. This structure exhibits significantly reduced short-channel effects (SCEs) when compared with the conventional DG MOSFET. Using two-dimensional (2-D) and two-carrier device simulation, the improvement in device performance focusing on threshold voltage dependence on channel length, electric field in the channel, subthreshold swing, and hot carrier effects, all of which can affect the reliability of complementary metal oxide semiconductor (CMOS) devices, was investigated.

One dimensional transport in silicon nanowire junction-less field effect transistors

Abstract: Junction-less nanowire transistors are being investigated to solve short channel effects in future CMOS technology. Here we demonstrate 8 nm diameter silicon nanowire junction-less transistors with metallic doping densities which demonstrate clear 1D electronic transport characteristics. The 1D regime allows excellent gate modulation with near ideal subthreshold slopes, on- to off-current ratios above 108 and high on-currents at room temperature. Universal conductance scaling as a function of voltage and temperature similar to previous reports of Luttinger liquids and Coulomb gap behaviour at low temperatures suggests that many body effects including electron-electron interactions are important in describing the electronic transport. This suggests that modelling of such nanowire devices will require 1D models which include many body interactions to accurately simulate the electronic transport to optimise the technology but also suggest that 1D effects could be used to enhance future transistor performance.

A Threshold Voltage Model of Silicon-Nanotube-Based Ultrathin Double Gate-All-Around (DGAA) MOSFETs Incorporating Quantum Confinement Effects

Abstract: In this paper, a quantum-mechanical threshold voltage model for ultrathin double gate-all-around DGAA MOSFETs has been developed by solving three-dimensional (3-D) Poisson's and 2-D Schrodinger's equations in the channel region. The parabolic potential approximation is considered for Poisson's equation solution, whereas a hollow cylindrical potential well in the channel region is assumed to solve Schrodinger's equation. Simple equations for the wave function and energy quantization in the channel of DGAA MOSFET have been formulated. Discretized energy levels have been used for channel charge calculation in subthreshold regime of device operation. The calculated channel charge is compared with a threshold charge to formulate the threshold voltage model. The effects of the device parameters such as the channel thickness, oxide thickness, doping, etc. on threshold voltage and DIBL have been extensively studied. The proposed model results have been verified by comparing with the numerical simulation results obtained from the 3-D device simulator Visual TCAD of Cogenda Int.

An 8b subthreshold hybrid thermal sensor with ±1.07°C inaccuracy and single-element remote-sensing technique in 22nm FinFET

Abstract: Thermal sensors are commonly used in modern highly dense systems-on-chip (SoC) to provide information about die temperature for thermal protection or performance optimization. To enable the deployment of multiple sensors in an SoC, the power and size of such sensors has been steadily reduced. Although most solutions are PNP-based [1-4], recently a low-power NPN-based current-mode thermal sensor [5] was implemented to meet the power and form-factor requirement with a robust architecture. However, since NPN devices are only available in a triple-well process, its use in low-cost dual-well processes is limited. This paper demonstrates a current-mode hybrid thermal sensor in an advanced 22nm FinFET process [6] based on subthreshold NMOS transistors and a parasitic PNP [7]. A simple voltage-based single-point soft-trimming was implemented to mitigate the sensitivity of the sensor to the subthreshold factor variability during manufacturing. Instead of placing the whole sensor system in multiple locations in a system, the hybrid architecture also supports single-element remote sensing. Only a 0.00021mm2 PNP device placed in the area of interest and a signal connection to the main sensor are then needed for temperature sensing. The sensor system achieves +/−1.07°C (±3σ) precision with 0.0043mm2 silicon area and 50uA current consumption from a 1V supply.

Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation

Abstract: In this paper, we investigate the retention time distribution of IBM's 65nm node embedded DRAM. We demonstrate that subthreshold current is the dominant leakage mechanism that determines data retention time, and the retention distribution can be attributed to array Vt variation. Based on this study, we present a new technique for characterization of across-chip Vt variation. The Vt median value and standard deviation of transfer devices within an eDRAM array are estimated by analyzing the retention characteristics. The evaluation results are confirmed by the parametric test data. The proposed method is fast and can be used to monitor Vt variation in both technology development and manufacture. The impact of array Vt spread on the retention and performance of eDRAM is discussed.