Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Dielectric pocket double gate junctionless FET: a new MOS structure with improved subthreshold characteristics for low power VLSI applications

Abstract: In this paper, we report the TCAD based simulation of a new double-gate junctionless FETs (DG-JLFETs) structure incorporating dielectric pockets (DPs) at the source and drain ends. The proposed structure not only improves the ON to OFF drain current ratio (by $${\sim }$$~900 %), subthreshold swing characteristics (by $${\sim }$$~12 %) and Drain Induced Barrier Lowering (DIBL) (by $${\sim }$$~56 %) over the conventional DG-JLFETs (i.e. without DPs), but also provides additional flexibility of performance optimization of the device by changing the length and thickness of the DPs. Since only little work has been carried out on the performance optimization of the JLFETs, the present work is believed to be very useful for designing the low-power VLSI circuits using DP-DG JLFETs with improved performance.

Semiconductor memory device with reduced leak current

Abstract: In a data holding mode, a potential on a substrate region in a memory cell array is fixed at the same level as that in a normal operation mode, and an absolute value of a bias voltage applied to a substrate region in a peripheral circuit is made larger than that in the normal operation mode. When an operation mode changes, a memory cell transistor substrate potential does not change, and therefore a potential on a storage node of a memory cell does not change, so that the storage data is stably held. A threshold voltage of an MOS transistor in the peripheral circuit increases in absolute value, and a subthreshold current is reduced. A current consumption is reduced in the data holding mode of a semiconductor memory device without adversely affecting storage data.

Advanced FinFET CMOS Technology: TiN-Gate, Fin-Height Control and Asymmetric Gate Insulator Thickness 4T-FinFETs

Abstract: We have successfully developed the advanced FinFET fabrication processes for materializing FinFET CMOS circuits. Using the developed technologies, we demonstrate the advanced TiN metal gate, fin-height controlled FinFET CMOS inverter with an excellent transfer performance, and the flexible threshold voltage, asymmetric gate insulator thickness four-terminal (4T) FinFET with a greatly improved subthreshold (S) slope, for the first time.

Analytical Model of Short-Channel Double-Gate JFETs

Abstract: In this paper, we propose a compact model of the short-channel double-gate (DG) JFETs, which are devices intended for low-power logic applications. In order to make the current equation continuous through all operating conditions from the subthreshold to well above the threshold without nonphysical fitting parameters, mobile carriers in depletion regions are considered. For describing the short-channel behavior, relevant parameters extracted from the 2-D analytical solution of Poisson's equation are used to modify long-channel equations. The field-dependent mobility, velocity saturation, channel-length modulation, and drain-induced barrier lowering are considered in the short-channel analysis. Models for the DG JFET are verified through numerically simulated current-voltage characteristics. Based on the model of the DG JFETs, the advantages of the DG JFETs over single-gate MOSFETs-which may have similar fabrication requirements-with the subthreshold regime are addressed.

Modelling of the nanoscale channel length effect on the subthreshold characteristics of junctionless field-effect transistors with a symmetric double-gate structure

Abstract: An analytical subthreshold current of deep nanoscale short channel junctionless field-effect transistors (JL FETs) with a symmetric double-gate (DG) structure has been proposed. It is derived from two-dimensional Poisson's equation using a variable separation technique. The proposed models can exactly describe the behaviour of subthreshold I–V characteristics with nanoscale channel length without any empirical fitting parameter. The model accounts for channel length, body thickness, gate oxide thickness and body doping concentrations. The models are verified by comparison with TCAD simulations and show good agreement.