Topic
Subthreshold conduction
About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.
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TL;DR: In this article, an unexpected sub-threshold swing degradation with increasing equivalent oxide thickness (EOT) was observed compared with the simulated results obtained under the assumption of ideal band-to-band tunneling.
Abstract: Tunnel field-effect transistors (TFETs) exhibiting a minimum subthreshold swing (SS) of 27 mV/decade were successfully fabricated using conventional planar HfO2/Si-gate-stack structures. However, an unexpected SS degradation with increasing equivalent oxide thickness (EOT) was observed compared with the simulated results obtained under the assumption of ideal band-to-band tunneling. We found that the poor subthreshold operation was governed by a thermally activated process, suggesting trap-assisted tunneling that occurs with traps near the metallurgical pn junction. Furthermore, we discuss the effect of the observed EOT-sensitive SS degradation on device production.
34 citations
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TL;DR: This brief presents a two-port disturb-free 9T subthreshold static random access memory (SRAM) cell with independent single-ended read bitline and write bitline (WBL) and cross-point data-aware write structure to facilitate robust subth threshold operation and bit-interleaving architecture for enhanced soft error immunity.
Abstract: This brief presents a two-port disturb-free 9T subthreshold static random access memory (SRAM) cell with independent single-ended read bitline and write bitline (WBL) and cross-point data-aware write structure to facilitate robust subthreshold operation and bit-interleaving architecture for enhanced soft error immunity. The design employs a variation-tolerant line-up write-assist scheme where the timing of area-efficient boosted write wordline and negative WBL are aligned and triggered/initiated by the same low-going global WBL to maximize the write-ability enhancement. A 72-kb test chip is implemented in United Microelectronics Corp. 40-nm low-power (40LP) CMOS. Full functionality is achieved for V $_{\mathrm {DD}}$ ranging from 1.5 to 0.32 V without redundancy. The measured maximum operation frequency is 260 MHz (450 kHz) at 1.1 V (0.32 V) and 25 °C. At 0.325 V and 25 °C, the chip operates at 600 kHz with 5.78 $\mu $ W total power and 4.69 $\mu $ W leakage power, offering $2\times $ frequency improvement compared with 300 kHz of our previous 72-kb 9T subthreshold SRAM design in the same 40LP technology. The energy efficiency (power/frequency/IO) at 0.325 V and 25 °C is 0.267 pJ/bit, a 23.7% improvement over the 0.350 pJ/bit of our previous design.
34 citations
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TL;DR: In this paper, a 3D drain-current model for double-gate or triple-gate silicon on insulator (SOI) metal-oxide-semiconductor field effect transistors is presented based on a physics-based 3D analysis.
Abstract: In this paper, we present a new compact drain-current model for double-gate or triple-gate silicon on insulator (SOI) metal-oxide-semiconductor field-effect transistors, which is based on a physics-based 3-D analysis. Explicit analytical model equations for the height of the potential barrier are derived in closed form from a 3-D model for the channel electrostatics without the need to introduce any fitting parameter. The device current is described by a superposition of a surface-channel current above threshold and a center current in the subthreshold region, accounting for the movement of the most leaky path in the device cross section. Comparison with Technology Computer Aided Design (TCAD) shows a good scalability of the model down to a gate length of 30 nm. Furthermore, the I-V characteristics are compared with measurements and obtain accurate results down to an effective channel length of 53 nm.
34 citations
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TL;DR: In this paper, the role of the elementary kaon production cross-section was investigated and the uncertainties introduced because of the poor knowledge of the latter near threshold were largely eliminated by considering kaon yield ratios.
34 citations
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04 Apr 1994TL;DR: In this article, the authors show that in a unilateral transistor (10, 70), a portion (37, 45) of a dopant layer (25, 30) between a source region (48, 51) and a drain region (49, 52) serves as a channel region and sets the voltage and leakage current.
Abstract: Insulated gate field effect transistors (10, 70) having process steps for setting the VT and a device leakage current which are decoupled from the process steps for providing punchthrough protection, thereby lowering a subthreshold swing. In a unilateral transistor (10), a portion (37, 45) of a dopant layer (25, 30) between a source region (48, 51) and a drain region (49, 52) serves as a channel region and sets the VT and the device leakage current. A halo region (34, 39) contains the source region (48, 51) and sets the punchthrough voltage. In a bilateral transistor (70), both a source region (83, 86) and a drain region (84, 87) are contained within halo regions (75, 74, 79, 81). A portion (76, 82) of a dopant layer (25, 30) sets the VT and a leakage current, whereas the halo region (75, 79) sets the punchthrough voltage.
34 citations