Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing

Abstract: A 2 muW, 100 kHz, 480 kb subthreshold SRAM operating at 0.2 V is demonstrated in a 130 nm CMOS process. A 10-T SRAM cell allows 1 k cells per bitline by eliminating the data-dependent bitline leakage. A virtual ground replica scheme is proposed for logic "0" level tracking and optimal sensing margin in read buffers. Utilizing the strong reverse short channel effect in the subthreshold region improves cell writability and row decoder performance due to the increased current drivability at a longer channel length. The sizing method leads to an equivalent write wordline voltage boost of 70 mV and a delay improvement of 28% in the row decoder compared to the conventional sizing scheme at 0.2 V. A bitline writeback scheme was used to eliminate the pseudo-write problem in unselected columns.

Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing

Abstract: As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations, traditional MOSFET scaling theory prescribes reducing supply and threshold voltages in proportion to device dimensions, a practice that induces an exponential increase in subthreshold leakage. As a result, leakage power has become comparable to dynamic power in current-generation processes, and will soon exceed it in magnitude if voltages are scaled down any further. Beyond this inflection point, multicore processors will not be able to afford keeping more than a small fraction of all cores active at any given moment. Multicore scaling will soon hit a power wall. This paper presents resistive computation, a new technique that aims at avoiding the power wall by migrating most of the functionality of a modern microprocessor from CMOS to spin-torque transfer magnetoresistive RAM (STT-MRAM)---a CMOS-compatible, leakage-resistant, non-volatile resistive memory technology. By implementing much of the on-chip storage and combinational logic using leakage-resistant, scalable RAM blocks and lookup tables, and by carefully re-architecting the pipeline, an STT-MRAM based implementation of an eight-core Sun Niagara-like CMT processor reduces chip-wide power dissipation by 1.7× and leakage power by 2.1× at the 32nm technology node, while maintaining 93% of the system throughput of a CMOS-based design.

Electrophoretic displays and systems for addressing such displays

Abstract: Electrophoretic displays include a light-emitting layer, a photoconductive layer, and an electrophoretic layer. The light-emitting layer may be an organic, light-emitting material, or organic, light-emitting diode, which is addressable using a multiplex addressing drive scheme. The impedance of the photoconductive layer is lowered when struck by light from the light-emitting layer. As a result of the lowered impedance of the photoconductive layer, the electrophoretic layer, which itself cannot be multiplexed, is addressed at a lower, subthreshold voltage.

Characterizing and modeling minimum energy operation for subthreshold circuits

Abstract: Subthreshold operation is emerging as an energy-saving approach to many new applications. This paper examines energy minimization for circuits operating in the subthreshold region. We show the dependence of the optimum V/sub DD/ for a given technology on design characteristics and operating conditions. Solving equations for total energy provides an analytical solution for the Optimum VDD and V/sub T/ to minimize energy for a given frequency in subthreshold operation. SPICE simulations of a 200K transistor FIR filter confirm the analytical solution and the dependence of the minimum energy operating point on important parameters.

Organic Thin-Film Transistors: Part I—Compact DC Modeling

Abstract: A generic analytical model for the current-voltage characteristics of organic thin-film transistors (OTFTs) is derived. Based on this generic model, a TFT compact dc model that meets the requirements for compact modeling, including for computer circuit simulators, is proposed. The models are fully symmetrical, and the TFT compact dc model covers all regimes of TFT operation-linear and saturation above threshold, subthreshold, and reverse biasing. The empirical fitting parameters are mostly eliminated from the characteristic equations. The developed models are also in close correspondence to several physical, parametric, and limiting models for current-voltage and mobility characteristics. An essential practical feature of the TFT compact dc model is that the model is both upgradable and reducible, allowing for easier implementation and modifications and also simultaneously allowing for separation of characterization techniques. This allows for systematic fitting of experimental data with large scattering in the values, but at the same time, preserving consistently the OTFT behavior in the model.