Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Analytical model for subthreshold conduction and threshold switching in chalcogenide-based memory devices

Abstract: Chalcogenide materials are receiving increasing interest for their many applications as active materials in emerging memories, such as phase-change memories, programmable metallization cells, and cross-point devices. The great advantage of these materials is the capability to appear in two different phases, the amorphous and the crystalline phases, with rather different electrical properties. The aim of this work is to provide a physically based model for conduction in the amorphous chalcogenide material, able to predict the current-voltage (I−V) characteristics as a function of phase state, temperature, and cell geometry. First, the trap-limited transport at relatively low currents (subthreshold regime) is studied, leading to a comprehensive model for subthreshold conduction accounting for (a) the shape of the I−V characteristics, (b) the measured temperature dependence, (c) the dependence of subthreshold slope on the thickness of the amorphous phase, and (d) the voltage dependence of the activation ener...

Threshold voltage shift in organic field effect transistors by dipole monolayers on the gate insulator

Abstract: We demonstrate controllable shift of the threshold voltage and the turn-on voltage in pentacene thin film transistors and rubrene single crystal field effect transistors (FET) by the use of nine organosilanes with different functional groups. Prior to depositing the organic semiconductors, the organosilanes were applied to the SiO2 gate insulator from solution and form a self-assembled monolayer (SAM). The observed shifts of the transfer characteristics range from −2to50V and can be related to the surface potential of the layer next to the transistor channel. Concomitantly the mobile charge carrier concentration at zero gate bias reaches up to 4×1012∕cm2. In the single crystal FETs the measured transfer characteristics are also shifted, while essentially maintaining the high quality of the subthreshold swing. The shift of the transfer characteristics is governed by the built-in electric field of the SAM and can be explained using a simple energy level diagram. In the thin film devices, the subthreshold re...

Subthreshold Regime has the Optimal Sensitivity for Nanowire FET Biosensors

Abstract: Nanowire field-effect transistors (NW-FETs) are emerging as powerful sensors for detection of chemical/biological species with various attractive features including high sensitivity and direct electrical readout. Yet to date there have been limited systematic studies addressing how the fundamental factors of devices affect their sensitivity. Here we demonstrate that the sensitivity of NW-FET sensors can be exponentially enhanced in the subthreshold regime where the gating effect of molecules bound on a surface is the most effective due to the reduced screening of carriers in NWs. This principle is exemplified in both pH and protein sensing experiments where the operational mode of NW-FET biosensors was tuned by electrolyte gating. The lowest charge detectable by NW-FET sensors working under different operational modes is also estimated. Our work shows that optimization of NW-FET structure and operating conditions can provide significant enhancement and fundamental understanding for the sensitivity limits ...

Modeling and sizing for minimum energy operation in subthreshold circuits

Abstract: This paper examines energy minimization for circuits operating in the subthreshold region. Subthreshold operation is emerging as an energy-saving approach to many energy-constrained applications where processor speed is less important. In this paper, we solve equations for total energy to provide an analytical solution for the optimum V/sub DD/ and V/sub T/ to minimize energy for a given frequency in subthreshold operation. We show the dependence of the optimum V/sub DD/ for a given technology on design characteristics and operating conditions. This paper also examines the effect of sizing on energy consumption for subthreshold circuits. We show that minimum sized devices are theoretically optimal for reducing energy. A fabricated 0.18-/spl mu/m test chip is used to compare normal sizing and sizing to minimize operational V/sub DD/ and to verify the energy models. Measurements show that existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits.

High performance fully-depleted tri-gate CMOS transistors

Abstract: Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.