Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Nonlinear Interaction between Shunting and Adaptation Controls a Switch between Integration and Coincidence Detection in Pyramidal Neurons

Abstract: The membrane conductance of a pyramidal neuron in vivo is substantially increased by background synaptic input. Increased membrane conductance, or shunting, does not simply reduce neuronal excitability. Recordings from hippocampal pyramidal neurons using dynamic clamp revealed that adaptation caused complete cessation of spiking in the high conductance state, whereas repetitive spiking could persist despite adaptation in the low conductance state. This behavior was reproduced in a phase plane model and was explained by a shunting-induced increase in voltage threshold. The increase in threshold allows greater activation of the M current (IM) at subthreshold potentials and reduces the minimum adaptation required to stabilize the system; in contrast, activation of the afterhyperpolarization current is unaffected by the increase in threshold and therefore remains unable to stop repetitive spiking. The nonlinear interaction between shunting and IM has other important consequences. First, timing of spikes elicited by brief stimuli is more precise when background spikes elicited by sustained input are prohibited, as occurs exclusively with IM-mediated adaptation in the high conductance state. Second, activation of IM at subthreshold potentials, which is increased in the high conductance state, hyperpolarizes average membrane potential away from voltage threshold, allowing only large, rapid fluctuations to reach threshold and elicit spikes. These results suggest that the shift from a low to high conductance state in a pyramidal neuron is accompanied by a switch from encoding time-averaged input with firing rate to encoding transient inputs with precisely timed spikes, in effect, switching the operational mode from integration to coincidence detection.

A Variation-Tolerant Sub-200 mV 6-T

Abstract: In this paper, we present a deep subthreshold 6-T SRAM, which was fabricated in an industrial 0.13 m CMOS technology. We first use detailed simulations to explore the chal- lenges of ultra-low-voltagememorydesign witha specificemphasis on the implications of variability. We then propose a single-ended 6-T SRAM design with a gated-feedback write-assist that remains robust deep in the subthreshold regime. Measurements of a test chip show that the proposed memory architecture functions from 1.2 V down to 193 mV and provides a 36% improvement in energy consumption over the previously proposed multiplexer-based subthreshold SRAM designs while using only half the area. Ad- justable footers and headers are introduced, as well as body bias techniques to extend voltage scaling limits.

Back-gated CMOS on SOIAS for dynamic threshold voltage control

Abstract: The simultaneous reduction of power supply and threshold voltages for low-power design without suffering performance losses will eventually reach the limit of diminishing returns as static leakage power dissipation becomes a significant portion of the total power consumption. This is especially acute in systems that are idling most of the time. In order to meet the opposing requirements of high performance at reduced power supply voltage and low-static leakage power during idle periods, a dynamic threshold voltage control scheme is proposed. A novel Silicon-On-Insulator (SOI)-based technology called Silicon-On-Insulator-with-Active-Substrate (SOIAS) was developed whereby a back-gate is used to control the threshold voltage of the front-gate; this concept was demonstrated on a selectively scaled CMOS process implementing discrete devices and ring oscillators. For a 250 mV switch in threshold voltage, a reduction of 3-4 decades in subthreshold leakage current was measured.

Unified complete MOSFET model for analysis of digital and analog circuits

Abstract: In this paper, we describe a complete MOSFET model developed for circuit simulation based on fully consistent physical concept. The model describes all transistor characteristics as a function of surface potentials, which are calculated iteratively at each applied voltage under the charge-sheet approximation. The key idea of this development is to put as much physics as possible into the equations describing the surface potentials. Since the model includes both the drift and the diffusion contributions, a single equation is valid from the subthreshold to the saturation regions. Contrary to the expectation, the results show that our semi-implicit model including the iteration procedures can even reduce the CPU time significantly in comparison with a conventional model similar to BSIM2 including short-channel effects. This is due to the consistent description of the model equations for all transistor characteristics, which results in more straightforward device equations, once the surface potentials have been computed.

A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V $_{\min}$ Lowering Techniques and Deep Sleep Mode

Abstract: A voltage scalable 0.26 V, 64 kb 8T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Utilization of the reverse short channel effect in a SRAM cell design improves cell write margin and read performance without the aid of peripheral circuits. A marginal bitline leakage compensation (MBLC) scheme compensates for the bitline leakage current which becomes comparable to a read current at subthreshold supply voltages. The MBLC allows us to lower Vmin to 0.26 V and also eliminates the need for precharged read bitlines. A floating read bitline and write bitline scheme reduces the leakage power consumption. A deep sleep mode minimizes the standby leakage power consumption without compromising the hold mode cell stability. Finally, an automatic wordline pulse width control circuit tracks PVT variations and shuts off the bitline leakage current upon completion of a read operation.