Topic
Subthreshold conduction
About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.
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TL;DR: In this paper, an analytical current-voltage model for 2D transition metal dichalcogenide (TMD) based field effect transistors (FETs) is presented.
Abstract: This paper presents an analytical current-voltage model specifically formulated for 2-dimensional (2D) transition metal dichalcogenide (TMD) semiconductor based field-effect transistors (FETs). The model is derived from the fundamentals considering the physics of 2D TMD crystals, and covers all regions of the FET operation (linear, saturation, and subthreshold) under a continuous function. Moreover, three issues of great importance in the emerging 2D FET arena: interface traps, mobility degradation, and inefficient doping have been carefully considered. The compact models are verified against 2-D device simulations as well as experimental results for state-of-the-art top-gated monolayer TMD FETs, and can be easily employed for efficient exploration of circuits based on 2D FETs as well as for evaluation and optimization of 2D TMD-channel FET design and performance.
129 citations
TL;DR: Return maps constructed from data show that both types of response are governed by the same deterministic one-dimensional description, with an unstable subthreshold fixed point largely accounting for the irregular intervals at moderate stimulation frequencies.
Abstract: Action potentials resulting from periodic stimulation of nerve axons occur at intervals that are irregular at moderate stimulation frequencies. Histograms of the intervals are multimodal, as seen in stochastic resonance. At higher stimulation frequencies, the action potentials are suppressed entirely, leaving only subthreshold dynamics. Return maps constructed from data show that both types of response are governed by the same deterministic one-dimensional description, with an unstable subthreshold fixed point largely accounting for the irregular intervals at moderate stimulation frequencies. [S0031-9007(96)00200-1]
128 citations
TL;DR: In this article, a lateral strained double-gate TFET (SDGTFET) is presented, which has a higher on-current, low leakage, low threshold voltage, excellent sub-threshold slope, and good short channel effects.
Abstract: Tunnel field effect transistor (TFET) devices are attractive as they show good scalability and have very low leakage current. However they suffer from low on-current and high threshold voltage. In order to employ the TFET for circuit applications, these problems need to be tackled. In this paper, a novel lateral strained double-gate TFET (SDGTFET) is presented. Using device simulation, we show that the SDGTFET has a higher on-current, low leakage, low threshold voltage, excellent subthreshold slope, and good short channel effects and also meets important ITRS guidelines.
128 citations
TL;DR: In this paper, a source pocket Si TFET is presented and successfully fabricated by laser annealing, which has enhanced lateral electric field across the source tunneling junction, resulting in a reduction of tunneling distance.
Abstract: To reduce the power consumption and improve the device performance in scaled CMOS integrated circuits, transistors with steep subthreshold swing (SS) is highly desirable. The tunnel field-effect transistor (TFET) based on the band-to-band tunneling has been suggested as a replacement to conventional MOSFETs. In order to improve the device performance of TFET, enhanced carrier transport across the tunneling junction is crucial. In this paper, source-pocket Si TFET is presented and successfully fabricated by laser annealing. This TFET has enhanced lateral electric field across the source tunneling junction, resulting in a reduction of tunneling distance. The experimental data of the proposed paper, for the first time, shows steep SS (46 mV/dec at 1 pA/μm), excellent ION/IOFF ratio ( <; 107), and improved output characteristics at T = 300 K due to the dramatic reduction of the tunneling resistance. Compared with other TFET works, the proposed method is efficient to improve the device performance on TFET.
127 citations
01 Feb 2008
TL;DR: The paper presents an SRAM array with bit interleaving and read scheme, fabricated in a 90nm CMOS technology, and the leakage power consumption is close to that of the 6T cell even though it has extra transistors in a cell.
Abstract: The paper presents an SRAM array with bit interleaving and read scheme. The SRAM test-chip is fabricated in a 90nm CMOS technology. For leakage comparison, 49 kb arrays are implemented for both the conventional 6T cell and 10T cell. The leakage power consumption of this SRAM is close to that of the 6T cell (between 0.96times and 1.1times) even though it has extra transistors in a cell. This is because the subthreshold leakage from the bitline to the cell node is drastically reduced by the stacking of devices in the leakage path. The design operates at 31.25 kHz with a 0.18 V supply. With more aggressive wordline boosting of 80 mV, the VDD scales down to 0.16 V at 0.16 V VDD, the operating frequency is 500 Hz and power consumption is 0.123 muW.
127 citations