Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Mechanism of device degradation in n- and p-channel polysilicon TFTs by electrical stressing

Abstract: The effects of electrical stress on hydrogenated n- and p-channel polysilicon thin-film transistors are discussed. The on-state caused the most significant degradation, whereas off-state and accumulation conditions resulted in negligible degradation. The on-state stress degraded the threshold voltage, trap state density, and subthreshold sharpness of both n- and p-channel devices toward perhydrogenated values, and the rates of degradation increased with stressing biases. The field-effect mobility and leakage current, however, were not degraded by stressing. The mechanism of device degradation may be attributed to the metastable creation of midgap states within the polysilicon channel, as opposed to gate dielectric charge trapping or interface state generation. >

An Ultra-Low-Power Memory With a Subthreshold Power Supply Voltage

Abstract: A 512times13 bit ultra-low-power subthreshold memory is fabricated on a 130-nm process technology. The fabricated memory is fully functional for read operation with a 190-mV power supply at 28 kHz, and 216 mV for write operation. Single bits are measured to read and write properly with VDD as low as 103 mV and 129 mV, respectively. The memory operates at a 1-MHz clock rate with a 310-mV power supply. This operating point has 1.197 muW power consumption, of which 0.366 muW is due to leakage and 0.831 muW is due to dynamic power dissipation. Analysis of the available fan-out or fan-in that can be supported at a given voltage is summarized. A number of circuit techniques are presented to overcome the substantially reduced on-to-off current ratios and the poor drive strength of transistors operating in subthreshold. These include a gated feedback memory cell, and hierarchical read and decode circuits. The memory is dynamic, with pseudo-static operation provided via self-timed control of the keeper transistors to mitigate increased variability manifested in subthreshold operation

Device optimization for digital subthreshold logic operation

Abstract: Digital circuits operated in the subthreshold region (supply voltage less than the transistor threshold voltage) can have orders of magnitude power advantage over standard CMOS circuits for applications requiring ultralow power and medium frequency of operation. Although the implication of technology scaling on subthreshold operation is not obvious (since an obsolete technology node can deliver the same performance as a scaled technology in subthreshold), it has been shown that technology scaling helps to reduce the supply-voltage and, hence, the power consumption at iso-performance. It is possible to implement subthreshold logic circuits using the standard transistors that are designed primarily for ultra high performance super-threshold logic design. However, an Si MOSFET so optimized for performance in the super-threshold regime is not the best device to use in the subthreshold domain. We propose device designs apt for subthreshold operation. Results show that the optimized device improves the delay and power delay product (PDP) of an inverter chain by 44% and 51%, respectively, over the normal super-threshold device operated in the subthreshold region.

The state-of-the-art of silicon-on-sapphire CMOS RF switches

Abstract: Silicon-on-Sapphire (SOS) CMOS FETs have many properties which are desirable for RF switch applications. By being manufactured on an insulating sapphire substrate, the bulk parasitic capacitances typical of CMOS FETs are eliminated. The SOS FET has a very low Ron-Coff product, allowing for low insertion loss and high isolation in high frequency applications. Despite the low breakdown voltage intrinsic to Si, SOS FETs can be stacked in series to withstand high voltages when biased in subthreshold. This work studies the tradeoffs of SOS RF switch design and compares SOS against other technologies such as GaAs and Si-based SOI. Also presented is a high power SP6T switch with insertion loss of 0.6 dB at 2 GHz and isolation of 40 dB at 2 GHz. The presented switch has the highest linearity reported to date of any SP6T switch with a P1dB of 20 W and OIP3 of <+70 dBm.

A Simple Subthreshold CMOS Voltage Reference Circuit With Channel- Length Modulation Compensation

Abstract: This brief presents a simple reference circuit with channel-length modulation compensation to generate a reference voltage of 221 mV using subthreshold of MOSFETs at supply voltage of 0.85 V with power consumption of 3.3 muW at room temperature using TSMC 0.18-mum technology. The proposed circuit occupied in less than 0.0238 mm 2 achieves the reference voltage variation of 2 mV/V for supply voltage from 0.9 to 2.5V and about 6 mV of temperature variation in the range from -20degC to 120 degC. The agreement of simulation and measurement data is demonstrated