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Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.


Papers
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Journal ArticleDOI
TL;DR: In this paper, a comprehensive large-signal MESFET model that provides a realistic description of measured characteristics over all operating regions is presented, it describes subthreshold conduction and breakdown.
Abstract: A comprehensive large-signal MESFET model that provides a realistic description of measured characteristics over all operating regions is presented, It describes subthreshold conduction and breakdown. It has frequency dispersion of both transconductance and drain conductance, and derates with power dissipation. All derivatives are continuous for a realistic description of circuit distortion and intermodulation. The model has improved descriptions of capacitance and bias dependence. It has small-signal S-parameter accuracy extended to a wide range of operating conditions. The model is implemented with new techniques for continuity and dispersion. These provide accurate prediction of circuit performance and also improve simulation speed.

100 citations

Journal ArticleDOI
TL;DR: In this paper, a simple analytical model that describes MOSFET operation in saturation from subthreshold to strong inversion is used to derive a new formulation of the intrinsic switching delay of the transistor.
Abstract: A simple analytical model that describes MOSFET operation in saturation from subthreshold to strong inversion is used to derive a new formulation of the intrinsic switching delay of the transistor. The proposed model follows the scaling trend of experimental ring-oscillator data better than the conventional CV/I metric. The historical trend of MOSFET performance scaling is examined, and it is shown that the continuous increase of the carrier velocity in the channel has been the main driver for the improved transistor performance with scaling. The dependence of velocity and mobility in recent strain-engineered devices is studied based on published experimental data, and a theory is proposed to justify this dependence. It is shown that the virtual-source velocity depends on low-field mobility more strongly than what was previously believed, in spite of the fact that state-of-the-art MOSFETs operate at 60%-65% of their ballistic limit. These observations will be used in Part II of this paper to explore the tradeoffs between key device parameters in order for the commensurate scaling of the device performance with its dimensional scaling to continue in the future high-performance CMOS generations.

100 citations

Journal ArticleDOI
TL;DR: In this paper, the potential variation in the channel obtained from analytical solution of three-dimensional (3-D) Poisson's equation is used to calculate the subthreshold current and threshold voltage of fin field effect transistors with doped and undoped channels.
Abstract: The potential variation in the channel obtained from analytical solution of three-dimensional (3-D) Poisson's equation is used to calculate the subthreshold current and threshold voltage of fin field-effect transistors with doped and undoped channels. The accuracy of the model has been verified by the data from 3-D numerical device simulator. The variation of subthreshold slope and threshold voltage with device geometry and doping concentration in the channel has been studied.

99 citations

Journal ArticleDOI
28 Mar 2018
TL;DR: In this article, a monolayer MoS2 FET with near-zero hysteresis reached 0.15% of the sweeping range of the gate bias, a record value observed so far in 2D FETs.
Abstract: While two-dimensional (2D) van der Waals (vdW) layered materials are promising channel materials for wearable electronics and energy-efficient field-effect transistors (FETs), large hysteresis and large subthreshold swing induced by either dangling bonds at gate oxide dielectrics and/or trap molecules in bubbles at vdW interface are a serious drawback, hampering implementation of the 2D-material based FETs in real electronics. Here, we report a monolayer MoS2 FET with near-zero hysteresis reaching 0.15% of the sweeping range of the gate bias, a record-value observed so far in 2D FETs. This was realized by squeezing the MoS2 channel between top h-BN layer and bottom h-BN gate dielectrics and further removing the trap molecules in bubbles at the vdW interfaces via post-annealing. By segregating the bubbles out to the edge of the channel, we also obtain excellent switching characteristics with a minimum subthreshold swing of 63 mV/dec, an average subthreshold slope of 69 mV/dec for a current range of four orders of magnitude at room temperature, and a high on/off current ratio of 108 at a small operating voltage (<1 V). Such a near-zero hysteresis and a near-ideal subthreshold limit originate from the reduced trap density of ~5.2 × 109 cm−2 eV−1, a thousand times smaller than previously reported values.

99 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023153
2022349
2021172
2020196
2019242
2018272