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Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.


Papers
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Journal ArticleDOI
TL;DR: In this article, a 2-mum gate length device with ZnO active layers was demonstrated with a drain-current ON/OFF ratio of 1012, a draincurrent density of 400 mA/mm, a field-effect mobility of 110 cm2/V ldr s, and a sub-threshold gate voltage swing of 109 m\/dec.
Abstract: We have developed ZnO thin-film transistor design and fabrication techniques to demonstrate microwave frequency operation with 2-mum gate length devices produced on GaAs substrates. Using SiO2 gate insulator and pulsed laser deposited ZnO active layers, a drain-current ON/OFF ratio of 1012, a drain-current density of 400 mA/mm, a field-effect mobility of 110 cm2/V ldr s, and a subthreshold gate voltage swing of 109 m\/dec were achieved. Devices with Ti-gate metal had current and power gain cutoff frequencies of 500 and 400 MHz, respectively.

87 citations

Journal ArticleDOI
TL;DR: Low current, high frequency trains of stimuli, when applied at a site presumed to be close to the reentrant circuit, provided a safe and effective method of terminating the common type of AV node reentrants tachycardia.

87 citations

Journal ArticleDOI
TL;DR: In this article, a parameter extraction methodology and a verification of a generic analytical model and a thin-film transistor (TFT) compact dc model for the currentvoltage characteristics of organic TFTs are presented.
Abstract: A parameter extraction methodology and a verification of a generic analytical model and a thin-film transistor (TFT) compact dc model for the current-voltage characteristics of organic TFTs are presented. The verification shows that the proposed models meet the requirements for compact modeling and for computer circuit simulators. The models are fully symmetrical, and the TFT compact dc model is validated in all regimes of operation-linear and saturation above threshold, subthreshold, and reverse biasing. Suitable characterization techniques for parameter extraction of mobility, threshold voltage, and contact resistance are provided. Approaches are elaborated for the essential practical feature of upgradability and reducibility of the TFT compact dc model, allowing for easier implementation and modification, as well as separation of characterization techniques.

87 citations

Journal ArticleDOI
TL;DR: The authors consider the determination of conditions when an excitable membrane can be considered linear and steady-state and deals with threshold for a space-clamped fiber, and the transient intracellular current.
Abstract: Examines the transmembrane voltage response of an unmyelinated fiber to a stimulating electric field from a point current source. For subthreshold conditions, analytic expressions for the transmembrane potential, v/sub m/, are developed that include the specific effects of fiber-source distance, h, and time from the onset of the stimulus, T. Suprathreshold effects are determined for two examples by extending the analytical results with a numerical model. The v/sub m/, response is a complex evolution in time, especially for small h, that differs markedly from the "activating function". In general, the subthreshold response is a good predictor of the wave shape of the suprathreshold v/sub m/ but a poor predictor of its magnitude. The subthreshold response also is a good (but not a precise) predictor of the region where excitation begins. >

87 citations

Journal ArticleDOI
TL;DR: An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage SRAM based on a flexible and extensible architecture that provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation is fabricated.
Abstract: An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage (ULV) SRAM based on a flexible and extensible architecture was fabricated on a 2.7 mm2 test chip in 65 nm low power CMOS. The processor cores are based on a custom standard cell library that was designed using a multiobjective approach to optimize noise margins, switching energy, and propagation delay simultaneously. The cores operate over a supply voltage range from 200 mV (best samples) to 1.2 V with clock frequencies from 10 kHz to 94 MHz at room temperature. The lowest energy consumption per cycle of 9.94 pJ is observed at 325 mV and 133 kHz. A 2 kb ULV SRAM macro achieves minimum energy per operation at averages of 321 mV (0.030 σ/μ), 567 fJ (0.037 σ/μ), and 730 kHz (0.184 σ/μ), for equal number of 32 b read/write operations. The off-chip performance and power management subsystem provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation.

87 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023153
2022349
2021172
2020196
2019242
2018272