Topic
Subthreshold conduction
About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.
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01 Jan 1993TL;DR: In this paper, the authors presented an analytical expression for sub-threshold current reduction in a decoded-driver by self-reverse biasing, which is inherently required for low-voltage, low-power, high-speed DRAM's for portable equipment.
Abstract: Analytical expressions are presented for subthreshold current reduction in a decoded-driver by self-reverse biasing, which is inherently required for low-voltage, low-power, high-speed DRAM's for portable equipment. The scheme involves inserting a switching MOS transistor between the driver circuits and its power supply line. The subthreshold current of the decoded-driver is reduced to the order of 10/sup -3/ in the practical temperature range (250-350 K) with 254 mV of self-reverse biasing voltage, while the delay time is only 3% more than in conventional schemes. The transition time of 1 ms from the operating state to the low subthreshold current state is sufficient to reduce the subthreshold current. The rapid recovery time of 1 ns from the low subthreshold current state does not interrupt the start of normal operation. The subthreshold current reduction was confirmed experimentally using a test chip fabricated with 0.25- mu m technology. >
85 citations
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TL;DR: By employing a bulk-driven technique and the MOS transistors working in the subthreshold region, the supply voltage and the power dissipation are reduced and a trimming circuit is adopted to compensate for the process-related reference voltage variation.
Abstract: We present a low-voltage low-power CMOS subthreshold voltage reference with no resistors and no bipolar junction transistors in a wide temperature range. The temperature stability is improved by second-order compensation. By employing a bulk-driven technique and the MOS transistors working in the subthreshold region, the supply voltage and the power dissipation are reduced. Moreover, a trimming circuit is adopted to compensate for the process-related reference voltage variation. The proposed voltage reference has been fabricated with the 0.18- $\mu\text{m} $ 1.8-V CMOS process. The measurement results show that the minimum power supply voltage is 0.45 V, the power consumption is 14.6 nW, the average temperature coefficient measured from $-40\ ^{\circ}\mbox{C} $ to 125 °C is 63.6 ppm/°C, and the line regulation is 1.2 mV/V in the power supply voltage ranging from 0.45 to 1.8 V. In addition, the chip area is 0.012 mm2.
85 citations
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TL;DR: In this article, a novel silicon solid-state photodetector structure utilizing the MOSFET subthreshold effect was conceived, developed, fabricated, and experimental results were obtained.
Abstract: A novel silicon solid-state photodetector structure utilizing the MOSFET subthreshold effect was conceived, developed, fabricated, and experimental results were obtained. This photodetector device, which can be integrated on the same chip with MOSFET circuits or CCD's, provides an analog voltage signal over a wide dynamic range. Fabricated photodetector devices and arrays showed experimentally, in the visible spectrum, an incoming radiation detection light intensity dynamic range of greater than 107. In addition, the novel photodetector device was used to realize CCD and self-scanned MOSFET linear arrays. In this paper, we describe in detail the theory of the new photodetector device and its applications to form linear imaging arrays. Finally, we present experimental results obtained on developed and fabricated devices and arrays.
85 citations
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IBM1
TL;DR: In this article, depletion mode MOSFET behavior at low temperatures, unusual changes in the threshold characteristics of the devices were observed, and the effectiveness of the donor implantation in producing a negative threshold voltage shift was significantly reduced at the same time the substrate sensitivity was substantially reduced.
Abstract: During the study of depletion mode MOSFET behavior at low temperatures, unusual changes in the threshold characteristics of the devices were observed First, the effectiveness of the donor implantation in producing a negative threshold voltage shift was significantly reduced At the same time the substrate sensitivity was found to be substantially reduced A third observation was the existence of an unusual structure in the subthreshold region of the device at low temperatures Computer simulation is used to explore these observations and to demonstrate that they are caused by impurity freezeout as temperature is reduced The computer simulation program, usable over the temperature range 50–350 K, is discussed, and a threshold definition suitable for numerical analysis of devices with arbitrary channel structures is developed
85 citations
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TL;DR: In this paper, a novel layer structure comprising Si/Si/sub 0.7/Ge/Sub 0.3/ virtual substrate (VS) offers improved performance advantages and a strain-compensated structure.
Abstract: Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si/sub 0.7/Ge/sub 0.3/ on an Si/sub 0.85/Ge/sub 0.15/ virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process.
85 citations