Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Improved subthreshold characteristics of n-channel SOI transistors

Abstract: It has been found that certain n-channel MOSFET's fabricated on silicon-on-insulator (SOI) substrates formed by oxygen implantation can have \log (I_{d}): V_{gs} , characteristics with very steep slopes in the subthreshold region. In contradiction to normal models for short-channel transistors on bulk silicon, the slope becomes steeper for shorter gate lengths or higher drain voltages. This effect is shown to be related to the kink in the output characteristics of transistors with floating islands.

Fatigue laser-induced damage in transparent materials

Abstract: We discuss the damage in transparent dielectrics produced by a train of laser pulses, each of which is less intensive than it is needed to cause the macroscopic breakdown. The problem under consideration includes both engineering and fundamental aspects. The practical interest is corresponded to the problem of long-term operation of optical elements in high-power laser systems. The main task of the theoretical analysis is to estimate the relative contribution of impurity-related and intrinsic processes into the phenomenon of `fatigue' (cumulative) damage. The experimental data concerning the subthreshold laser-induced damage are reviewed here, together with the proposed to date multi-shot damage mechanisms, which are described in the main features.

Heterojunction Vertical Band-to-Band Tunneling Transistors for Steep Subthreshold Swing and High on Current

Abstract: We propose a heterojunction vertical tunneling field-effect transistor and show using self-consistent ballistic quantum transport simulations that it can provide very steep subthreshold swings and high on current, thereby improving the scalability of TFETs for high performance. The turn-on in the pocket region of the device is dictated by the modulation of heterojunction barrier height. The steepness of turn-on is increased because of simultaneous onset of tunneling in the pocket and the region underneath and also due to the contribution of vertical tunneling in the pocket to the current. These factors can be engineered by tuning heterojunction band offsets.

A low-power wide dynamic range envelope detector

Abstract: We report a 75-dB 2.8-/spl mu/W 100-Hz-10-kHz envelope detector in a 1.5-/spl mu/m 2.8-V CMOS technology. The envelope detector performs input dc insensitive voltage-to-current converting rectification followed by novel nanopower current-mode peak detection. The use of a subthreshold wide linear range transconductor allows greater than 1.7-V/sub pp/ input voltage swings. We show theoretically that the optimal performance of this circuit is technology independent for the given topology and may be improved only by spending more power due to thermal noise rectification limits. A novel circuit topology is used to perform 140-nW peak detection with controllable attack and release time constants. We demonstrate good agreement of experimentally measured results with theory. The envelope detector is useful in low-power bionic implants for the deaf, hearing aids, and speech-recognition front-ends.

Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation

Abstract: Supply voltage scaling is one of the easiest ways to reduce energy dissipation. Therefore, researchers have considered subthreshold logic as a promising option to achieve ultra low energy dissipation. However, circuit propagation delay is extremely sensitive to PVT variations under subthreshold operation. Hence, large delay margin is required for successful operation of conventional synchronous designs. Since leakage energy contributes to a substantial portion of total energy dissipation in subthreshold operation, the leakage energy dissipated for the required delay margin degrades energy efficiency significantly. In addition, even small intra-die variations result in large clock skew and hence, it is difficult to efficiently handle timing issues such as the setup and the hold time violations. In this work, we explore asynchronous design approach to address these challenges in subthreshold operation. We employ critical-path replica to generate completion signals of combinational logic blocks and use classical four-phase handshaking for communication between pipeline flip-flops. Since the proposed design approach uses only local clock buffers, it is easier to handle timing problems compared to synchronous designs. We compared iso-yield minimum energy dissipation of two design approaches (synchronous and asynchronous) in an inverter chain. Despite leakage overhead due to pad delay of critical-path delay line and ?return-to-zero? time of four-phase handshaking, the proposed asynchronous design shows 71% energy savings compared to its synchronous counterpart. To demonstrate subthreshold operation of the proposed design approach, we fabricated an 8-tap FIR filter in 90 nm CMOS. Measured oscilloscope plots of handshaking and output bus signals show that the design operates successfully below 300 mV. We also measured energy consumption of the FIR filter from 19 test chips-the average was 4.64 pJ and the standard deviation was 0.3526 pJ.