Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

An Output-Capacitor-Free Adaptively Biased Low-Dropout Regulator With Subthreshold Undershoot-Reduction for SoC

Abstract: This paper presents an output-capacitor-free adaptively biased low-dropout regulator with subthreshold undershoot-reduction (ABSTUR LDR) for SoC power management applications. Techniques of adaptive biasing (AB) and Miller compensation with Q-reduction are employed to achieve low-voltage high-precision regulation with extended loop bandwidth while maintaining low quiescent current and high current efficiency. The pass transistor is designed to work in the linear region at heavy load to save silicon area, and a symmetrically matched current-voltage mirror is used to implement the AB scheme with accurate current sensing for the full load range. The dedicated STUR circuit, which is low-voltage compatible and consumes very low current in the steady state, is inserted to momentarily but exponentially increase the gate discharging current of the pass transistor when the LDR output has a large undershoot due to a large step up of the load current. Undershoot voltage is hence dramatically reduced. Stability of the ABSTUR LDR is thoroughly analyzed and tradeoffs between the undershoot-reduction strength and the light load stability are discussed. Features of the proposed ABSTUR LDR are experimentally verified by a prototype fabricated in a standard 0.35-μm CMOS process.

Interface Traps in InAs Nanowire Tunnel-FETs and MOSFETs—Part I: Model Description and Single Trap Analysis in Tunnel-FETs

Abstract: This paper and the companion work present a full quantum study of the influence of interface traps on the I-V characteristics of InAs nanowire Tunnel-field effect transistors (FETs) and MOSFETs. To this purpose, we introduced a description of interface traps in a simulator based on non equilibrium Green's function formalism, employing an 8 × 8 k·p Hamiltonian and accounting for phonon-scattering. In our model, traps can affect the I-V curves of the transistors both by modifying the device electrostatics and by directly participating the carrier transport. This paper investigates the impact of single trap on the I-V characteristics of Tunnel-FETs by varying the trap energy level, its volume and position, as well as the working temperature. Our 3-D self-consistent simulations show that: 1) even a single trap can deteriorate the inverse subthreshold slope of a nanowire InAs Tunnel-FET; 2) shallow traps have the largest impact on subthreshold slopes; and 3) the inelastic phonon-assisted tunneling through interface traps results in a temperature dependence of the otherwise temperature-independent Tunnel-FETs I-V characteristics.

Artificial Synaptic Conductances Reduce Subthreshold Oscillations and Periodic Firing in Stellate Cells of the Entorhinal Cortex

Abstract: Previous work has established that stellate cells of the medial entorhinal cortex produce prominent intrinsic subthreshold oscillations in the voltage response concentrated within the theta range (3-7 Hz). It has been speculated that these oscillations play an important role in vivo in establishing network behavior both in the entorhinal cortex and hippocampus. Consequently, it is important to investigate under what conditions theta oscillations in stellate cells can be generated and whether the spike-train power spectral density (PSD) also carries power at theta. We investigated the ability of stellate cells to generate theta oscillations in the presence of generic in vivo-like patterns of stimulation. Inputs were Poisson process-driven excitatory and inhibitory synaptic conductances or currents, introduced via dynamic clamp. We analyzed the subthreshold membrane oscillations and spike-train behavior in the presence of comparable synaptic conductance- or current-mediated membrane fluctuations. In the presence of conductance-based synapses, subthreshold oscillations are highly attenuated or entirely eliminated. Conversely, with current-based synapses stellate cells retain their ability to generate subthreshold oscillations in the theta band. These results also extend into the spiking regime, where only under current-based synapses does the PSD of the spike train show a prominent peak at theta. Furthermore, the peak in the spike-train PSD and spike clustering results from an increased probability of firing after a spike afterhyperpolarization and not directly from subthreshold oscillatory dynamics as has been previously suggested. Our results suggest that subthreshold oscillations may contribute less to in vivo response properties than has been hypothesized.

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

Abstract: This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage V DD and threshold voltage V TH in active and standby modes. In the active mode, on the basis of delay monitoring results, either V DD control or V TH control is selected to avoid any oscillation problem between them. In V DD control, on the basis of delay monitoring results, V DD is adjusted so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. In V TH control, on the basis of power monitoring results, V TH is adjusted so as to maintain a certain switching current I SW /leakage current I LEAK ratio known to indicate minimum power consumption. In the standby mode, the precision of power monitoring (which detects optimum body bias by comparing subthreshold current I SUBTH to substrate current I SUB ) is improved by taking into consideration both the effects of lowering V DD and the effects of the presence of gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that use of the proposed power monitoring results in the successful minimizing of power consumption. It does so by making it possible to: 1) maintain the I SW /I LEAK ratio in the active mode and 2) detect optimum body bias conditions (I SUBTH = I SUB ) within an error of less than 20% with respect to actual minimum leakage current values in the standby mode.

Undoped-Body Extremely Thin SOI MOSFETs With Back Gates

Abstract: We present a detailed study of gate length scalability and device performance of undoped-body extremely thin silicon-on-insulator (ETSOI) MOSFETs with back gates. We show that short channel control improves with the application of back bias via a decrease in the electrostatic scaling length as the subthreshold charges move toward the front gate. We demonstrate that, even for undoped ETSOI devices with ~8-nm SOI thickness, the improvement in short channel control with the application of a back bias translates to 10% higher drive current, 10% shorter gate lengths, and, consequently, 20% lower extrinsic gate delay at a fixed off-state current of 100 nA/mum and a back oxide electric field of 1.5 MV/cm (0.5 MV/cm SOI field).