Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Influence of phonon scattering on the performance of p-i-n band-to-band tunneling transistors

Abstract: Power dissipation has become a major obstacle in performance scaling of modern integrated circuits and has spurred the search for devices operating at lower voltage swing. In this letter, we study p-i-n band-to-band tunneling field effect transistors taking semiconducting carbon nanotubes as the channel material. The on current of these devices is mainly limited by the tunneling barrier properties, and phonon-scattering has only a moderate effect. We show, however, that the off current is limited by phonon absorption assisted tunneling, and thus is strongly temperature dependent. Subthreshold swings below the 60mV∕decade conventional limit can be readily achieved even at room temperature. Interestingly, although subthreshold swing degrades due to the effects of phonon scattering, it remains low under practical biasing conditions.

Indium Oxide Thin-Film Transistors Fabricated by RF Sputtering at Room Temperature

Abstract: Thin-film transistors (TFTs) were fabricated using an indium oxide (In2O3) thin film as the n-channel active layer by RF sputtering at room temperature. The TFTs showed a thickness-dependent performance in the range of 48-8 nm, which is ascribed to the total carrier number in the active layer. Optimum device performance at 8-nm-thick In2O3 TFTs had a field-effect mobility of 15.3 cm2 · V-1 · s-1, a threshold voltage of 3.1 V, an ON-OFF current ratio of 2.2 × 108, a subthreshold gate voltage swing of 0.25 V · decade-1, and, most importantly, a normally OFF characteristic. These results suggest that sputter-deposited In2O3 is a promising candidate for high-performance TFTs for transparent and flexible electronics.

Comparison of MOSFET-threshold-voltage extraction methods

Abstract: The difference in MOSFET threshold voltages caused by the difference in the extraction method is studied, by measuring and analyzing its dependencies on channel length, substrate voltage and drain voltage. It is found that the standard deviation of the difference between threshold voltages caused by the difference in the extraction method is less than that of the threshold voltage itself in a wafer. The dependencies of the threshold voltage on channel length, extracted from the drain current data around the threshold voltage, however, show different behavior from those extracted from the drain current data only in the subthreshold region or only in the ON region. It is considered that “channel-length modulation” causes this different behavior and, therefore, that those extraction methods are not desirable.

SPICE Modeling for Small Geometry MOSFET Circuits

Abstract: VLSI circuit simulation requires computationally efficient MOSFET models. In this paper, VLSI circuit simulator models for the active device and some important passive devices are described. A quasi-physical short channel MOSFET current model is derived. This current model contains both above-threshold and subthreshold components. The values of the model parameter are extracted automatically from measured I-V data. The reduction in process information in this representation is shown to be tolerable using a proper quantization of the geometry and device type space. Narrow width effect is also included. A charge conserving MOSFET capacitor model is also given. The importance of the parasitic devices on VLSI circuit is shown and a model for the fringing capacitance due to finite gate thickness is introduced. A "process box" based on the statistical variation of parameters is extracted from a completely automated device characterization system. Experimental results indicate that the width and length are independent random variables. This statistical information allows the circuit response to be simulated across the process window.

5.8 A 9.3nW all-in-one bandgap voltage and current reference circuit

Abstract: Ultra-low-power (ULP) sensor technologies for the future internet of things have presented challenges in ULP implementation of reference circuits while keeping traditional requirements of stable performance. For voltage reference circuits, as an essential block in SoCs to generate various internal supply voltages, the bandgap voltage-reference (BGVR) scheme has been widely used since it provides a well-defined value with strong immunity to process/voltage/temperature variations. Nanowatt-consuming BGVR circuits have been recently proposed using a capacitor network [4] and a leakage-based proportional-to-absolute-temperature (PTAT) circuit [5]. On the other hand, the current reference circuit that is required to set internal bias current still presents difficulties in achieving both stable performance and ULP consumption. The general approach to building a current reference is to use a BGVR with additional resistors for V-to-I conversion. Though it can provide a well-defined stable current reference, it also requires excessively large resistance for ULP consumption. Another approach is a CMOS-based current reference circuit that tries to make the exponential term in the subthreshold current equation constant or temperature-independent, hence reducing process and temperature dependencies. While CMOS reference circuits have achieved ULP implementations, the current is still determined by a number of process and design parameters, resulting in large sensitivity to process variations. This paper presents a sub-10nW bandgap-reference (BGR) circuit that implements both voltage and current references in one circuit. The BGR circuit is implemented with a 0.18µm CMOS process and generates voltage and a current references of 1.238V and 6.64nA while consuming 9.3nW. The voltage and current references show standard deviations of 0.43% and 1.19% with temperature coefficients of 26ppm/°C and 283ppm/°C, respectively.