Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Threshold Displacement Energies and Subthreshold Displacements in Copper and Gold Near 10°K

Abstract: These experiments were undertaken to determine more precisely the minimum energy Td needed to displace an atom from its lattice position. The resistivity increase as a function of integrated flux was measured at various electron energies. The damage‐production curve, thus obtained, was the sum of two components. The first contribution is due to direct displacement processes. From a projection of this component to zero, we estimate TdCu=16–19 eV and TdAu=33–36 eV. The second contribution, the subthreshold events, are due to various ``soft spots'' associated with unavoidable impurities in the nominally 99.999% pure copper and gold specimens. It has been shown that displacements near dislocations do not contribute in a significant manner. It has been further shown that the formation of light‐atom interstitials can contribute to subthreshold processes. While this does not conclusively prove that subthreshold processes in nominally pure copper and gold are due to the presence of light‐atom impurities, we believe this to be the most probable subthreshold mechanism.

A 0.8-V 230- $\mu$ W 98-dB DR Inverter-Based $\Sigma \Delta$ Modulator for Audio Applications

Abstract: This paper presents a ΣΔ modulator based on a gain-boost class-C inverter for audio applications. The gain-boost class-C inverter behaves as a low-voltage subthreshold amplifier and boosts its dc gain for the high-precision requirement. Meanwhile, an on-chip body bias is used to compensate the performance degradation of the inverter at a slow process corner or low supply voltage. The proposed inverter-based modulator is fabricated in a 65-nm mixed-signal CMOS process with a die area of 0.3 mm 2. The experimental chip achieves 91-dB peak signal-to-noise-plus-distortion ratio (SNDR), 94-dB signal-to-noise ratio (SNR) and 98-dB dynamic range (DR) over a 20-KHz audio band with a 5-MHz sampling frequency and a 0.8-V supply voltage consuming only 230-μW power, which demonstrates that the gain-boost class-C inverter is particularly suitable for low-voltage micro-power high-resolution applications.

Semianalytical Modeling of Short-Channel Effects in Lightly Doped Silicon Trigate MOSFETs

Abstract: A simple analytical expression of the 3-D potential distribution along the channel of lightly doped silicon trigate MOSFETs in weak inversion is derived, based on a perimeter-weighted approach of symmetric and asymmetric double-gate MOSFETs. The analytical solution is compared with the numerical solution of the 3-D Poisson's equation in the cases where the ratios of channel length/silicon thickness and channel length/channel width are ges 2. Good agreement is achieved at different positions within the channel. The perimeter-weighted approach fails at the corner regions of the silicon body; however, by using corner rounding and undoped channel to avoid corner effects in simulations, the agreement between model and simulation results is improved. By using the extra potential induced in the silicon film due to short-channel effects, the subthreshold drain current is determined in a semianalytical way, from which the subthreshold slope, the drain-induced barrier lowering, and the threshold voltage are extracted.

High Electrical Performance of Wet-Processed Indium Zinc Oxide Thin-Film Transistors

Abstract: We developed thin-film transistors (TFTs) that use solution-processed amorphous indium zinc oxide for the channels in an all-photolithographic process. The transistors, which operate in depletion mode, have excellent transfer characteristics, including saturation mobility of 6.57 cm2/ V·s, threshold voltages of - 0.30 V, turn-on voltages of -1.50 V, on/off ratios of 109, and inverse subthreshold slopes of 0.15 V/dec. We measured the time, temperature, gate voltage, and drain-voltage dependence of the threshold voltage shift, which was 2.16 V under stress conditions. This is nearly the same as that of conventional amorphous silicon TFTs.

Design and Iso-Area $V_{\min}$ Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS

Abstract: In this brief, a 9T bit cell is proposed to enhance write ability by cutting off the positive feedback loop of a static random-access memory (SRAM) cross-coupled inverter pair. In read mode, an access buffer is designed to isolate the storage node from the read path for better read robustness and leakage reduction. The bit-interleaving scheme is allowed by incorporating the proposed 9T SRAM bit cell with additional write wordlines (WWL/WWLb) for soft-error tolerance. A 1-kb 9T 4-to-1 bit-interleaved SRAM is implemented in 65-nm bulk CMOS technology. The experimental results demonstrate that the test chip minimum energy point occurs at 0.3-V supply voltage. It can achieve an operation frequency of 909 kHz with 3.51-W active power consumption.