Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

CMOS-SOI-MEMS Transistor for Uncooled IR Imaging

Abstract: This paper reports the design, fabrication technology, post-CMOS micromachining and characterization of CMOS-silicon-on-insulator (SOI)-microelectromechanical system (MEMS) transistors. The thermally isolated micromachined CMOS-SOI-MEMS transistor reported here is designed for uncooled infrared (IR) sensing and is dubbed here as ldquoTMOS.rdquo The measured dc and noise electrical characteristics of the as-processed (virgin) transistor as well as those of the post-CMOS-MEMS-processed transistor (TMOS) are reported and compared. In particular, the threshold voltage temperature dependence and the temperature coefficient of current (TCC) at subthreshold are reported. The results indicate that the post-CMOS-MEMS processing does not degrade the performance of the transistors. The electrooptical performance of the TMOS is characterized and reported. With TCC on the order of 4%-10%, depending on the gate voltage, responsivity of 40 mA/W, noise equivalent power on the order of several tens of picowatts, and calculated noise equivalent temperature difference on the order of 64 mK, this uncooled IR sensor in standard CMOS-SOI technology may provide a high performance at a lower cost compared to state-of-the-art uncooled sensors based on bolometers implemented in non-CMOS materials like vanadium oxide or amorphous silicon.

Tuning the threshold voltage of MoS2 field-effect transistors via surface treatment.

Abstract: Controlling the threshold voltage (Vth) of a field-effect transistor is important for realizing robust logic circuits. Here, we report a facile approach to achieve bidirectional Vth tuning of molybdenum disulfide (MoS2) field-effect transistors. By increasing and decreasing the amount of sulfur vacancies in the MoS2 surface, the Vth of MoS2 transistors can be left- and right-shifted, respectively. Transistors fabricated on perfect MoS2 flakes are found to exhibit a two-fold enhancement in mobility and a very positive Vth (18.5 ± 7.5 V). More importantly, our elegant hydrogen treatment is able to tune the large Vth to a small value (∼0 V) without any performance degradation simply by reducing the atomic ratio of S : Mo slightly; in other words, it creates a certain amount of sulfur vacancies in the MoS2 surface, which generate defect states in the band gap of MoS2 that mediates conduction of a MoS2 transistor in the subthreshold regime. First-principles calculations further indicate that the defect band's edge and width can be tuned according to the vacancy density. This work not only demonstrates for the first time the ease of tuning the Vth of MoS2 transistors, but also offers a process technology solution that is critical for further development of MoS2 as a mainstream electronic material.

High-performance InGaZnO thin-film transistors with high-k amorphous Ba0.5Sr0.5TiO3 gate insulator

Abstract: We report on high-performance n-channel thin-film transistors (TFTs) fabricated using amorphous indium gallium zinc oxide (a-IGZO) and amorphous Ba0.5Sr0.5TiO3 (a-BST) as the channel and gate dielectric layers, respectively. a-BST∕a-IGZO TFTs achieve low-voltage operation with a high saturation mobility value of 10±1cm2∕Vs, excellent subthreshold slopes of 0.06±0.01V/decade, a low threshold voltage of 0.5±0.1V, and a high on-off current ratio up to 8×107 (W∕L=1000μm∕5μm) at 3V. The high capacitance density of a-BST (145±2nF∕cm2) and the small contact resistance, smaller than the channel resistance, are responsible for the high performance of these TFTs.

Bias Stress Stability of Solution-Processed Zinc Tin Oxide Thin-Film Transistors

Abstract: The effects of bias stress on spin-coated zinc tin oxide (ZTO) transistors are investigated. Applying a positive bias stress results in the displacement of the transfer curves in the positive direction without changing the field-effect mobility or the subthreshold behavior, while a negative stress has no effect on the threshold voltage shift. Device instability appears to be a consequence of the charging and discharging of the temporal trap states at the interface and in the ZTO channel region. All the stressed devices recover their original characteristics after 10 min at room temperature. Furthermore, the inkjet-printed transistor yields similar bias stress effects as those observed in their spin-coated counterparts but has a greater shift in the threshold voltage. Microstructural evidence in conjunction with Rutherford backscattering spectroscopy confirms that severe instability is attributed to the presence of nanopores in the inkjet-printed channel layer.

On the temperature coefficient of the MOSFET threshold voltage

Abstract: The temperature coefficient of the threshold voltage of the most common types of MOSFET devices has been measured and analyzed in terms of the underlying device physics. Owing to differences in gate contact potential and anomalies of the substrate backbias effect, the above coefficient has a typical value for each type. In particular for a compensated device, such as a CMOS p-channel MOSFET, the value of the temperature coefficient is relatively large (up to 3 mV/degree).