Subthreshold conduction

About: Subthreshold conduction is a research topic. Over the lifetime, 6343 publications have been published within this topic receiving 131957 citations. The topic is also known as: Subthreshold leakage.

Stable room temperature deposited amorphous InGaZnO4 thin film transistors

Abstract: Enhancement-mode amorphous indium gallium zinc oxide (α-IGZO) channel thin film transistors (TFTs) with a 6μm gate length and a 100μm gate width were fabricated on glass substrates by rf magnetron sputtering near room temperature. The resistivities of the α-IGZO films were controlled from 10−1to103Ωcm by varying the deposition power of 75–300W. The n-type carrier concentration in the channel was 6.5×1017cm−3. The gate oxide was 90-nm-thick SiNx, deposited by plasma enhanced chemical vapor deposition at 70°C. The bottom-gate TFTs had saturation mobility of ∼17cm2V−1s−1 and the drain current on-to-off ratio of ∼>105, a subthreshold gate-voltage swing of ∼0.5Vdecade−1, and a threshold voltage of 2.1V. In the TFT with a gate length of 6μm and a gate width of 100μm, the relative change of saturation mobility and threshold voltage was less than ±1.5% after 500h aging time at room temperature. This demonstrates that α-IGZO films are promising semiconductor materials for long-term-stable transparent TFT applications.

Suppression of leakage current in Schottky barrier metal–oxide–semiconductor field-effect transistors

Abstract: In this article we investigate the subthreshold behavior of PtSi source/drain Schottky barrier metal–oxide–semiconductor field-effect transistors. We demonstrate very large on/off ratios on bulk silicon devices and show that slight process variations can result in anomalous leakage paths that degrade the subthreshold swing and complicate investigations of device scaling.

Low-Temperature Solution Processing of AlInZnO/InZnO Dual-Channel Thin-Film Transistors

Abstract: In this letter, we proposed solution-processed AlInZnO (AIZO)/InZnO (IZO) dual-channel thin-film transistors to realize both proper switching behavior and competitive device performance at the low annealing temperature of 350°C. A thin IZO layer provides a higher carrier concentration, thereby maximizing the charge accumulation and yielding high saturation mobility μsat, whereas a thick AIZO layer controls the charge conductance resulting in suitable threshold voltage Vth. We therefore obtain excellent device characteristics at 350°C with μsat of 1.57 cm2/V ·s, Vth of 1.28 V, an on/off ratio of ~1.4 × 107, and a subthreshold gate swing of 0.59 V/dec.

Picowatt, 0.45–0.6 V Self-Biased Subthreshold CMOS Voltage Reference

Abstract: In this paper, a self-biased temperature-compensated CMOS voltage reference operating at picowatt-level power consumption is presented. The core of the proposed circuit is the self-cascode MOSFET (SCM) and two variants are explored: a self-biased SCM (SBSCM) and a self-biased NMOS (SBNMOS) voltage reference. Power consumption and silicon area are remarkably reduced by combining subthreshold operation with a self-biased scheme. Trimming techniques for both circuits are discussed aiming at the reduction of the process variations impact. The proposed circuits were fabricated in a standard 0.18- $\mu \text{m}$ CMOS process. Measurement results from 24 samples of the same batch show that both circuits herein proposed can operate at 0.45/0.6 V minimum supply voltage, consuming merely 55/184 pW at room temperature. Temperature coefficient (TC) around 104/495 ppm/°C across a temperature range from 0 to 120 °C was measured. Employment of a trimming scheme allows a reduction of the average TC to 72.4/11.6 ppm/°C for the same temperature range. Both variants of the proposed circuit achieve a line sensitivity of 0.15/0.11 %/V and a power supply rejection better than −44/−45 dB from 10 to 10 kHz. In addition, SBSCM and SBNMOS prototypes occupy a silicon area of 0.002 and 0.0017 mm2, respectively.

Drain-induced barrier-lowering analysis in VSLI MOSFET devices using two-dimensional numerical simulations

Abstract: In recent publications the drain-induced barrier-lowering (DIBL) effect has been included in the determination of the drain current of short-channel MOSFET's by way of analytical expressions The validity of these published expressions has not been verified so far for small-geometry devices of different parameters Further, the relationship between the threshold voltage shift and the barrier lowering due to the DIBL effect has not been clarified in the literature In our present paper we carried a detailed study of the drain-induced barrier lowering in ion-implanted 1-µm VLSI MOSFET devices, leading to a better understanding and clarification of the fundamental mechanisms involved in the DIBL variation and its effect on the threshold voltage and subthreshold current Further, we found that the calculated DIBL parameters of the analytical model reported in the literature do not agree with the numerically computed values Hence we determined a set of new geometry parameters η and B/A for the DIBL threshold relationship that can be used with the analytical model Our work stresses the necessity of the use of two-dimensional numerical simulations when accurate evaluation of the DIBL effect in short-channel MOSFET's is required Also, our results should be useful for calibrating existing analytical MOSFET models In addition, our data and method could be used as a design tool for performance optimization of micrometer and submicrometer devices