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Subthreshold slope

About: Subthreshold slope is a research topic. Over the lifetime, 3014 publications have been published within this topic receiving 70424 citations.


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Journal ArticleDOI
TL;DR: In this paper, a dual material gate (DMG) was applied to a tunnel field effect transistor (TFET) to simultaneously optimize the on-current, the off-current and the threshold voltage.
Abstract: In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the threshold voltage and also improve the average subthreshold slope, the nature of the output characteristics, and immunity against the drain-induced barrier lowering effects. We demonstrate that, if appropriate work functions are chosen for the gate materials on the source side and the drain side, the TFET shows a significantly improved performance. We apply the technique of DMG in a strained double-gate TFET with a high-k gate dielectric to show an overall improvement in the characteristics of the device, along with achieving a good on-current and an excellent average subthreshold slope. The results show that the DMG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses, and power supply levels to achieve significant gains in the overall device characteristics.

382 citations

Proceedings ArticleDOI
08 Dec 2002
TL;DR: The I-MOS as discussed by the authors uses modulation of the breakdown voltage of a gated p-i-n structure in order to switch from the OFF to the ON state and vice versa.
Abstract: One of the "fundamental" problems in the continued scaling of MOSFETs is the 60 mV/decade room temperature limit in subthreshold slope. In this paper, we report initial studies on a new kind of transistor, the I-MOS. The I-MOS uses modulation of the breakdown voltage of a gated p-i-n structure in order to switch from the OFF to the ON state and vice versa. Since impact-ionization is an abrupt function of the electric field (or the carrier energy), simulations show that the device has a subthreshold slope much lower than kT/q. Simulations also show that it is indeed possible to make complementary circuits with switching speeds comparable to or exceeding CMOS. Experimental results on a silicon based prototype verify the basic concept and show very steep subthreshold slopes with high speed turn-on and turn-off. Lower bandgap materials are also being investigated to reduce the value of the breakdown voltage and permit lower voltage operation.

367 citations

Journal ArticleDOI
TL;DR: In this article, single-crystal organic p-type field effect transistors (OFETs) with the field effect hole mobility of 8 cm2/Vs, substantially higher than that observed in thin-film OFETs, are presented.
Abstract: We report on the fabrication and characterization of single-crystal organic p-type field-effect transistors (OFETs) with the field-effect hole mobility mu \~ 8 cm2/Vs, substantially higher than that observed in thin-film OFETs. The single-crystal devices compare favorably with thin-film OFETs not only in this respect: the mobility for the single-crystal devices is nearly independent of the gate voltage and the field effect onset is very sharp. Subthreshold slope as small as S = 0.85 V/decade has been observed for a gate insulator capacitance Ci = 2 +- 0.2 nF/cm2. This corresponds to the intrinsic subthreshold slope Si = SCi at least one order of magnitude smaller than that for the best thin-film OFETs and amorphous hydrogenated silicon (a-Si:H) devices.

352 citations

Journal ArticleDOI
TL;DR: To the best of the knowledge, this is the first report of all 2D transparent TFT fabricated on flexible substrate along with the highest mobility and current ON-OFF ratio.
Abstract: In this article, we report only 10 atomic layer thick, high mobility, transparent thin film transistors (TFTs) with ambipolar device characteristics fabricated on both a conventional silicon platform as well as on a flexible substrate. Monolayer graphene was used as metal electrodes, 3–4 atomic layers of h-BN were used as the gate dielectric, and finally bilayers of WSe2 were used as the semiconducting channel material for the TFTs. The field effect carrier mobility was extracted to be 45 cm2/(V s), which exceeds the mobility values of state of the art amorphous silicon based TFTs by ∼100 times. The active device stack of WSe2–hBN–graphene was found to be more than 88% transparent over the entire visible spectrum and the device characteristics were unaltered for in-plane mechanical strain of up to 2%. The device demonstrated remarkable temperature stability over 77–400 K. Low contact resistance value of 1.4 kΩ-μm, subthreshold slope of 90 mv/decade, current ON–OFF ratio of 107, and presence of both electr...

327 citations

Journal ArticleDOI
Joerg Appenzeller1, Yu-Ming Lin1, Joachim Knoch, Zhihong Chen1, Phaedon Avouris1 
TL;DR: In this article, three different carbon nanotube (CN) field effect transistor (CNFET) designs are compared by simulation and experiment, and the authors explore the possibility of using CNs as gate-controlled tunneling devices.
Abstract: Three different carbon nanotube (CN) field-effect transistor (CNFET) designs are compared by simulation and experiment. While a C-CNFET with a doping profile similar to a "conventional" (referred to as C-CNFET in the following) p-or n-MOSFET in principle exhibits superior device characteristics when compared with a Schottky barrier CNFET, we find that aggressively scaled C-CNFET devices suffer from "charge pile-up" in the channel. This effect which is also known to occur in floating body silicon transistors deteriorates the C-CNFET off-state substantially and ultimately limits the achievable on/off-current ratio. In order to overcome this obstacle we explore the possibility of using CNs as gate-controlled tunneling devices (T-CNFETs). The T-CNFET benefits from a steep inverse subthreshold slope and a well controlled off-state while at the same time delivering high performance on-state characteristics. According to our simulation, the T-CNFET is the ideal transistor design for an ultrathin body three-terminal device like the CNFET.

320 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202341
2022126
2021125
2020139
2019139
2018146