Topic
Subthreshold slope
About: Subthreshold slope is a research topic. Over the lifetime, 3014 publications have been published within this topic receiving 70424 citations.
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TL;DR: In this paper, the authors proposed n-and p-type tunnel field effect transistors (T-FETs) based on heterostructure Si/intrinsic-SiGe channel layer, which exhibit very small subthreshold swings, as well as low threshold voltages.
Abstract: In this paper, novel n- and p-type tunnel field-effect transistors (T-FETs) based on heterostructure Si/intrinsic-SiGe channel layer are proposed, which exhibit very small subthreshold swings, as well as low threshold voltages. The design parameters for improvement of the characteristics of the devices are studied and optimized based on the theoretical principles and simulation results. The proposed devices are designed to have extremely low off currents on the order of 1 fA/mum and engineered to exhibit substantially higher on currents compared with previously reported T-FET devices. Subthreshold swings as low as 15 mV/dec and threshold voltages as low as 0.13 V are achieved in these devices. Moreover, the T-FETs are designed to exhibit input and output characteristics compatible with CMOS-type digital-circuit applications. Using the proposed n- and p-type devices, the implementation of an inverter circuit based on T-FETs is reported. The performance of the T-FET-based inverter is compared with the 65-nm low-power CMOS-based inverter, and a gain of ~104 is achieved in static power consumption for the T-FET-based inverter with smaller gate delay.
306 citations
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TL;DR: In this paper, a double-gate junctionless tunnel field effect transistor (JL-TFET) is proposed and investigated, which uses two isolated gates (Control-Gate, P-Gate) with two different metal work-functions to behave like a TFET.
Abstract: In this letter, a double-gate junctionless tunnel field effect transistor (JL-TFET) is proposed and investigated. The JL-TFET is a Si-channel heavily n-type-doped junctionless field effect transistor (JLFET), which uses two isolated gates (Control-Gate, P-Gate) with two different metal work-functions to behave like a tunnel field effect transistor (TFET). In this structure, the advantages of JLFET and TFET are combined together. The simulation results of JL-TFET with high- $k$ dielectric material (TiO2) of 20-nm gate length shows excellent characteristics with high $I_{{\rm ON}}/I_{{\rm OFF}}$ ratio $(\sim 6\times 10^{8})$ , a point subthreshold slope (SS) of ${\sim}{\rm 38}~{\rm mV}$ /decade, and an average SS of ${\sim}{\rm 70}~{\rm mV}$ /decade at room temperature, which indicates that JL-TFET is a promising candidate for a switching performance.
301 citations
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TL;DR: In this article, the stability of thin film transistors incorporating sputtered ZnO as the channel layer is investigated under gate bias stress, while negative stress results in a negative shift.
Abstract: The stability of thin film transistors incorporating sputtered ZnO as the channel layer is investigated under gate bias stress. Positive stress results in a positive shift of the transfer characteristics, while negative stress results in a negative shift. Low bias stress has no effect on the subthreshold characteristics. This instability is believed to be a consequence of charge trapping at/near the channel/insulator interface. Higher biases and longer stress times cause degradation of the subthreshold slope, which is thought to arise as a consequence of defect state creation within the ZnO channel material. After all stress measurements, the devices recover their original characteristics at room temperature without any annealing.
301 citations
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IBM1
TL;DR: In this paper, an experimental and modeling study of charge trapping related threshold voltage shifts in Al2O3 and HfO2 n-type field effect transistors (nFET) is reported.
Abstract: An experimental and modeling study of charge trapping related threshold voltage shifts in Al2O3 and HfO2 n-type field effect transistors (nFET) is reported. The dependence of threshold voltage, subthreshold slope, and gate leakage currents on stressing time and injected charge carrier density are investigated as a function positive bias stress voltage and temperature. Based on experimental data, a model for trapping of charges in the existing traps is developed. The model is similar to SiO2 charge trapping models with one exception. Unlike SiO2 models, the model assumes a continuous distribution in trapping capture cross sections. The model predicts that threshold voltage would increase with a power law dependence on stressing time and injected charge carrier density (Ninj) in the initial stages of stressing. The model calculates threshold voltage shifts as a function of stress time and Ninj, thereby provides estimates of threshold voltage shifts after 10 years lifetime. It also provides insights into the...
300 citations
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01 Dec 2012TL;DR: In this paper, a leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time, and a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages.
Abstract: A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, < 65mV/dec subthreshold slope and <40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.
284 citations