Showing papers on "Switched capacitor published in 1986"

Analog MOS Integrated Circuits for Signal Processing

Abstract: Transformation Methods. MOS Devices as Circuit Elements. MOS Operational Amplifiers. Switched-Capacitor Filters. Nonfiltering Applications of Switched-Capacitor Circuits. Nonideal Effects in Switched-Capacitor Circuits. Systems Considerations and Applications. Index.

Transfer functions for switched-capacitor and wave digital filters

Abstract: Closed-form expressions are presented for amplitude-oriented low-pass, high-pass, and bandpass sampled-data transfer functions suitable for realization as 1) switched-capacitor lossless discrete integrator (LDI) ladder filters, or 2) wave digital filters. Other types of realizations are also possible, such as those employing voltage inverter switches (VIS's), the recently introduced switched-capacitor "voltage wave" filters, and standard recursive digital realizations. The filters possess optimum equirippie (or maximally flat) passbands and monotonic stopbands with arbitrary selectivity. The low-pass and high-pass cases are derived from distributed passive prototype functions, but the more important bandpass functions are quite novel, appearing here for the first time.

Switched-capacitor high-Q bandpass filters for IF applications

Abstract: Experimental results for a sixth-order switched-capacitor bandpass filter with a selectivity Q of 55 at a center frequency of 3.1 MHz are presented. A simple noise analysis of active bandpass filters composed of coupled identical resonators is introduced to explain the dynamic range reduction in high-Q active filters resulting from loose high-Q couplings between resonators. Theoretical predictions of noise in coupled resonator-type bandpass filters agree well with measured results. The prototype chip occupies 2 mm/SUP 2/ and dissipates 45 mW with a single 5-V supply.

A switched-capacitor interface for intelligent capacitive transducers

Abstract: A novel switched-capacitor circuit has been developed for interfacing capacitive transducers with digital systems. It consists of a differential integrator and a cyclic analog-to-digital converter (ADC). The capacitive transducer is first charged in proportion to its capacitance. This charge is next compared with that stored on a reference capacitor and their difference is converted to a voltage by a differential integrator. The sensitivity of this capacitance-to-voltage conversion is controlled by the rate of the charge accumulation. A binary output is obtained from the resultant voltage by analog-to-digital conversion. The whole operation is insensitive to parasitic capacitances, offset voltages of op amps, and the capacitor values involved in the circuit. Thus the proposed circuit permits an accurate differential capacitance measurement. An error analysis has shown that the resolution as high as 14 bits can be expected by realizing the circuit in a monolithic IC form. Besides the accuracy, it features the small device count integrable onto a small chip area. The circuit is thus suited particularly for the on-chip interface. Its application to a humidity sensor is also presented.

Evaluation of Switching Concerns Associated with 345 KV Shunt Capacitor Applications

Abstract: This paper presents the most significant results of a comprehensive Transient Network Analyzer study evaluating approximately 2500 MVAr of 345 kV switched capacitor banks throughout central eastern and southeastern New York. The study evaluated various concerns associated with switched shunt capacitor applications. These concerns include transient overvoltages at the switched capacitor and other locations during normal and abnormal capacitor bank switchings. The paper evaluates surge arrester duties, switching device requirements, current limiting reactors, and design requirements to avoid possible severe overvoltages.

Switched-capacitor algorithmic digital-to-analog converters

Abstract: Novel switched-capacitor circuits for algorithmic digital-to-analog conversion are described. The conversion process is insensitive both to the offset voltages of op-amps and to parasitic capacitances. The capacitance mismatch errors are also minimized because only a small number of unit capacitors are used. An error analysis is presented that shows an accuracy greater than 10-bits can be obtained using present MOS technologies. Besides being very accurate, the new converters possess the important feature of being integrable using only a minimal amount of chip area.

Switched-capacitor filter having digitally-programmable capacitive element

Abstract: A method and circuitry for time-sharing a digitally-programmable capacitive element, particularly in conjunction with a switched-capacitor filter circuit. The method includes: selecting a first capacitance value for the capacitive element; initializing the charge on the capacitive element; connecting the capacitive element to first preselected nodes of an electronic circuit; disconnecting the capacitive element from the first preselected nodes of after any charge transfer has substantially been completed; changing the capacitance of the capacitive element to a new desired value; initializing the charge on the capacitive element; and then connecting the capacitive element to other preselected nodes of the electronic circuit. A biquad switched-capacitor filter circuit is configured to use such method in its operation.

A scalable high-performance switched-capacitor filter

Abstract: Switched-capacitor filters tend to display reduced performance when implemented at reduced feature size because of higher KT/C and 1/f noise, and reduced operational amplifier gain and swing. Descriptions are given of circuit solutions to certain performance degradations associated with technology scaling, including chopper stabilization, and class AB differential operational amplifier architecture. An experimental fifth-order elliptic PCM low-pass filter, using 3-/spl mu/m CMOS technology, achieved an area of 200 mil per pole. Typical measured results for a /spl plusmn/2.5-V power supply are a dynamic range of 87 dB and a power supply rejection ratio of 40 dB over 1-MHz range.

Liquid crystal display control device

Abstract: A liquid crystal display control device, in accordance with the present invention, for supplying a voltage signal to drive a liquid crystal display unit comprises a boosting circuit, and a segment signal circuit and/or a common signal circuit. The boosting circuit includes a dc power supply first capacitor connected between a plurality of first group switches and to be connected in parallel to said dc power supply when the first group switches are operated, a plurality of second group switches, second boosting capacitor connected between the other polarity of the dc power supply and one end of the other switch of the second group switches. One of the second group switches is connected between one polarity of the power supply and one end of the first capacitor. A third electronic switching means is connected to the boosting circuit in parallel to the second capacitor for discharging the voltage charged in the second capacitor. Therefore, a voltage signal having a predetermined amplitude and polarity for driving the LCD display unit is charged in the second capacitor when the first and second switches are selectively operated and it is discharged when a power interruption occurs.

d.c. Block capacitor circuit for rejection of d.c. offset

Abstract: A d.c. block capacitor circuit suitable as an integrated circuit in that it requires only one pin for the connection of an external capacitor. The circuit has particular, but not exclusive, application to direct conversion receivers. The circuit comprises an operational amplifier (10) having an inverting and a non-inverting input and an output. A pair of resistors (12, 14) having values R1, R1', respectively, connect the respective amplifier inputs to a signal input (16). The amplifier has a feedback resistor (18) having a value R2 connected between the inverting input and the output. Another resistor (20) having a value R2'and a capacitor (22) are connected between the non-inverting input and either and same or different voltage reference point(s). The values of the resistors (12, 14, 18, 20) are selected so that the ratio of R2':R1' equals the ratio R2:R1. Any d.c. offset present in the input signal is rejected by the circuit so that the output therefrom comprises the signal centered on the reference voltage.

Electrical filter with adjustable RC product

Abstract: A continuous time electrical filter fabricated as an integrated circuit includes capacitors (CO,CN) and resistors (R1,R2). Since capacitors and resistors are difficult to integrate with accurately defined values a trimming circuit is provided which operates switches (S1-SN) to select appropriate ones of the capacitors (CN) to accurately define the cut-off frequency of the filter. The trimming circuit comprises a capacitor (TC2) which is charged through a resistor TR1 during a first period and which is discharged in incremental steps by a capacitor (TC1). The number of incremental steps is counted by a counter (11) and transferred to a register (13). The outputs (S1-SN) of the register control the switches (S1-SN). Instead of adjusting the value of the capacitors in the filter, the values of the resistors may be adjusted. If this is done a convenient procedure is to short out selected portions of the resistors. More than one capacitor or resistor may be adjusted using a single counter and register.

Switched-capacitor gain stage with reduced sensitivity to finite amplifier gain and offset voltage

Abstract: A new switched-capacitor gain stage is presented that exhibits reduced sensitivity to operational amplifier gain and offset voltage. In addition, the design employs fewer switches and capacitors than previous techniques, and is less sensitive to parasitic capacitance effects. It should find wide application in A/D, D/A and other analogue arithmetic building blocks.

Switched capacitor summing amplifier

Abstract: A switch capacitor summing amplifier is disclosed having a coupling means to couple desired signals to the active amplifier in response to an enable signal. The coupling is performed in synchronism to the "odd" phase of the sampling signals thereby improving noise, transient and DC offset performance while minimizing switch impedance sensitivity.

Differential CMOS comparator for switched capacitor applications

Abstract: A differential input circuit for a switched capacitor CMOS voltage comparator is provided which minimizes offset voltages by configuring the load devices to utilize a single switched capacitor biasing network initialized from internally-generated bias voltages, while configuring the initialization switches for the differential input devices to also utilize internally-generated bias voltages such that the offset voltages are stored on the input capacitors. The power supply rejection performance of the voltage comparator is also optimized by connecting parallel load devices of opposite switching topology such that the same input impedance is seen at both load terminals.

High-frequency switched-capacitor filter using unity-gain buffers

Abstract: The implementation of high-frequency switched-capacitor filters using unity-gain amplifiers in a balanced configuration is described. The effect of parasitic capacitances is analyzed for different structures, single-ended and balanced. Experimental results from a third-order elliptic filter integrated in a standard NMOS process are presented.

A novel switched-capacitor four-quadrant analog multiplier-divider and some of its applications

Abstract: The design of a general-purpose, MOS switched-capacitor multiplier-divider based on the time-division concept is described. This four-quadrant circuit has been implemented using only CMOS switches, three operational amplifiers, capacitors, and a logic inverter gate without any other electronic components. The transfer characteristic νo=kνxνy/νw of this circuit is only dependent upon external voltages and the ratio of capacitors. An experimental circuit has been built and tested. The results are in close agreement with theoretical predictions. Applications of this circuit to a root-mean-square measuring device and a frequency multiplier are also presented.

Switched capacitor filter for low voltage applications

Abstract: An improved switched capacitor circuit configuration is disclosed which exhibits improved low voltage supply operation and improved charge injection cancellation performance. In the preferred embodiment of a switched capacitor integrator, the improvement is realized by the particular configuration of a switched tub switch on the input, single N-channel devices at the summing junction, skewing the analog ground V AG downward, and delaying the clock signals to turn off the switches at the summing junction before the charge injection of the switched tub switch is realized.

Switched capacitor adaptive line equalizer

Abstract: A switched capacitor adaptive line equalizer for use in digital communication system adapted to receive input signals at a plurality of signal rates and to supply equalized output signals. Input signals are sent through a switched capacitor equalizer which includes a low-pass filter in order to control the frequency band of the input signals and a variable gain action which selectively sets a prescribed √f characteristic in response to the output of the low-pass filter. A control circuit responsive to the output of the switched capacitor equalizer and the input signal rate selectively adjusts to the characteristic of the switched capacitor equalizer means. Input signals are processed on a time division basis in two channels of the variable gain section, to select the operating characteristic on one of the channels while another operation is performed on the other channel.

A switched-capacitor digital capacitance meter

Abstract: A digital capacitance meter has been developed based on the switched-capacitor cyclic analog-to-digital (A/D) converter. It consists of the analog arithmetic and sample/hold (S/H) circuits. The arithmetic circuit first samples the capacitance to be measured in a form of its proportional voltage. This voltage is then converted into a binary number by the A/D converter. The whole operation is insensitive to parasitic capacitances, offset voltages of op amps, and the capacitance mismatch involved in the circuit. Therefore, the proposed meter permits an accurate capacitance measurement. Error analysis shows that 12-bit accuracy can be expected by realizing the meter in an IC form. A prototype meter built using discrete components and examples of measurement are also given.

Switched capacitor induction motor drive

Abstract: A switched capacitor, induction motor drive circuit wherein a switched capacitor (54, 56, 58) in parallel with the induction motor load at each output terminal (70, 72, 74) is provided for commutation or switching of the main output inverter elements (S-1 to S-6) thereby protecting the switching elements from excessive voltage during switching or commutation operation in combination with a unique switching control circuit (G-1 to G-6) which enables minimal voltage switching elements to be used and which eliminates the need for anti-parallel rectifiers in the inverter output stage. Alternate forms of the switching control circuit are disclosed. Regeneration induced power control circuits for dissipating or returning the power to the input lines are dislosed.

Inductive proximity switch having switched capacitor for controlling hysteresis

Abstract: An inductive proximity switch which consists of an oscillator with an externally controllable resonant circuit as well as of a switching amplifier controllable by the oscillator. It further has a feed or biasing circuit for the oscillator and the switching amplifier. Connected in parallel with the capacitor of the resonant circuit is a capacitor with an electronic switch, the electronic switch being responsive to the output of the switching amplifier. Thereby a simple switching hysteresis is obtained.

Differential switched capacitor integrator using a single integration capacitor

Abstract: A differential switched capacitor type integrator, particularly useful for building analog sampled-data switched capacitor filters, utilizes a single integration capacitor (or array of unitary capacitors connected in parallel) instead of the two distinct integration capacitors required in the known differential integrators. The number of the required capacitors is therefore reduced to one half in comparison to that required in accordance with the prior art.

On the implementation of fully differential switched-capacitor ladder filters

Abstract: Three fully differential switched-capacitor (SC) circuit equivalents of the standard single-ended two-integrator loop are investigated. Of particular interest is the use of these circuit blocks in the implementation of the ladder networks generated by the exact design method of Datar and Sedra.

Device for measuring the ratio of two low value capacities

Abstract: A device for measuring the ratio between a first capacitor and a second capacitor in which first and second switches are provided for selectively conducting a signal, therethrough based on a control signal. A capacity switching device receives the two capacitors, and includes a third switch for switching between these two capacitors. A control device controls the first and second switches to conduct in phase opposition to one another, and the third switch to connect the first and second capacitors separately and successively between the first and second switches. An integrator is connected to the output of the capacity switching device to integrate the output signal, and a capacity ratio measuring circuit is provided to detect the capacity ratio. In this way, detection of capacity ratio can be performed independent of the switching currents for the switches, the biasing current for the integrating amplifier, and any other biasing currents.

Switched capacitor circuit

Abstract: PURPOSE:To improve the accuracy of arithmetic operation as a switched capacitor circuit by distributing threshold voltage between a source and a drain in an MOSTr and connecting the MOSTr so that threshold voltage on the side connected to a capacitor is increased. CONSTITUTION:A switched capacitor circuit is constituted by an NMOSTr1 and a capacitor 2 for holding, the threshold voltage Vth of the Tr1 is distributed, and the Tr1 is connected so that the output side (the side connected to the capacitor 2) is increased. When a fall time to OFF from the ON of gate voltage is smaller than a time constant determined by a channel resistor and the capacitor 2, a channel disappears from the output side having high Vth. Consequently, channel charges mostly flow in to the input side, and only predetermined charges through overlapping capacitance remain in the capacitor 2, thus resulting in approximately zero of gain errors harmful on circuit constitution. Accordingly, the accuracy of arithmetic operation as the switched capacitor circuit is improved.

Fully differential bilinear integrator for SC filters

Abstract: A fully differential bilinear SC integrator, which can be used for SC filter realisations, is proposed. It is parasitic-insensitive and particularly useful in SC filters simulating analogue ladder networks. The design of these filters is different from the commonly used ones, and leads to filters with better sensitivity properties than earlier versions. Realisation of a third-order highpass filter, bilinearly transformed from the continuous-time to the discrete-time domain, is shown as an example.

Selective linear phase switched-capacitor filters modelled on classical structures

Abstract: Exact analytic techniques are given for the design of straysinsensitive lossless discrete integrator (LDI) switched-capacitor low-pass and high-pass filters, with phase linearity taken into consideration. An improved synthesis algorithm is also presented for the low-pass case. The given solutions appear for the first time in relation to switched-capacitor filters, but they rely on classical techniques in the area of passive (distributed) networks and cannot be obtained from lumped-element filters. Due to the importance of the topic and the paucity of useful results, parts of the paper are written in a review-like semi-tutorial style, in order to make the design techniques accessible to as wide a readership as possible. This paper, together with [2] and [4], constitute a comprehensive procedure for the exact design of LDI low-pass and high-pass filters with or without phase linearity; thus completing the picture for these important classes of switched-capacitor filters.

Signal transmission circuit

Abstract: A signal transmission circuit includes a switched capacitor and a control circuit. The switched capacitor includes a capacitor and a plurality of switching means. The control circuit controls the frequency or level of a control signal to be applied to the switching means of the switched capacitor. By varying the frequency of the control signal with the control circuit, the equivalent resistance of the switched capacitor can be varied. By controlling the level of the control signal with the control circuit, at least one of the plurality of switching means is held in the "off" state thereof, to substantially inhibit the signal transmission of the switched capacitor.

Programmable switched-capacitor low-pass ladder filters

Abstract: Switched-capacitor filters with digitally programmable capacitor arrays (DPCAs) offer a solution to the diverse needs to the market for audio-frequency high-order low-pass filters. Cascading switched-capacitor biquads which contain binary or geometrically weighted DPCAs are not a viable way to produce precision high-order responses, because of the errors introduced by capacitance quantization. To overcome this problem, a ladder-based structure is proposed. It uses DPCAs tailored to provide exactly the capacitances required to realize a restricted but useful set of responses. A simple procedure for synthesizing such filters is presented and illustrated with a detailed example. A CMOS prototype chip which provides eight seventh-order responses was fabricated. A 3-bit word programs its response: elliptic (with four different selectivities), Chebyshev, inverse Chebyshev, Butterworth, or modified Bessel (modified to have stopband notches). Experimental results are included which show that with this design philosophy, performance is not sacrificed for programmability.