Showing papers on "Switched capacitor published in 1987"

Charge injection in analog MOS switches

Abstract: Charge injection in MOS analog switches, also called pass transistors or transmission gates, is approached by using the continuity equation. Experimental results show the negligible influence of substrate current which leads to a unidimensional model. An easy-to-handle simplified model is deduced and its predictions compared to the injection obtained by measurements. It is shown that this model, which can be used to implement various strategies to reduce charge injection, is valid in any realistic situation.

Analog MOS integrated circuits for signal processing

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Measurement and analysis of charge injection in MOS analog switches

Abstract: The analysis has been extended to the general case including signal-source resistance and capacitance. Universal plots of percentage channel charge injected are presented. Normalized variables are used to facilitate usage of the plots. The effects of gate voltage falling rate, signal-source level, substrate doping, substrate bias, switch dimensions, as well as the source and holding capacitances are included in the plots. A small-geometry switch, slow switching rate, and small source resistance can reduce the charge injection effect. On-chip test circuitry with a unity-gain operational amplifier, which reduces the disturbance imposed by measurement equipment to a minimum, is found to be an excellent monitor of the switch charge injection. The theoretical results agree with the experimental data.

Switched-capacitor circuits with reduced sensitivity to amplifier gain

Abstract: A new technique for reducing the effect of finite amplifier gain in switched-capacitor circuits is described. The principle is to perform a preliminary charge transfer operation preceding every desired charge transfer operation, thus obtaining a close approximation of the finite gain error which is stored and subsequently used for correction. This provides excellent suppression of the finite gain effect, independent of the relationship between the clock rate and the signal frequencies. The technique is quite general in nature and can be applied in a wide variety of switchedcapacitor circuits. Its major applications will be in precision analog signal processing circuits like precision amplifiers, A/D and D/A converters, and analog arithmetic building blocks. Simulation studies indicate that this technique has the potential to reduce the amplifier gain requirements in such circuits by one to two orders of magnitude. This would simplify amplifier design and increase the high-frequency capability of these circuits.

Switched-capacitor neural networks

Abstract: A neural network implementation is proposed, consisting of switches, capacitors and inverters. A number of potentially attractive features of the implementation are pointed out.

A switched-capacitor charge-balancing analog-to-digital converter and its application to capacitance measurement

Abstract: An analog-to-digital converter is developed based on the charge-balancing principle. It consists of a switched-capacitor integrator, comparator, and digital logic circuit. Driven by the two phase clock, the integrator accumulates consecutively the incremental signal charge while extracting the quantized reference charge from the accumulated signal charge each time its output becomes positive, to keep their charge balance. The ratio between the accumulated and extracted frequencies for a given period of time then provides the digital representation of an input analog signal. A conversion accuracy higher than 14 bits can be expected from its integrated realization because the offset voltage and the finite open-loop gain of an op-amp and the parasitic capacitance have no effect upon the conversion process. It also features a small device-count integrate onto a very small chip area. Some applications are also presented to demonstrate its validity.

Switched capacitor filter

Abstract: A biquadrature switched capacitor filter having differential input/output integrator amplifiers (12,34) and switched capacitor networks (16,28,36,40). The differential outputs of one amplifier (12) are crossed and connected to the switched capacitor networks (36,40) of the other amplifier (34) to provide a negative capacitance effect. Feedforward capacitors (70,72) are switched to prevent the stage input signals (IN+, IN-) from being coupled during certain phases of a biphase nonoverlapping clock. In high-pass applications, a feedback capacitor (134, 136) makes positioning of pole and zero responses easy. Amplifier bandwidth is controlled by switched capacitors (148, 152) connected to the amplifiers during certain clock phases.

Chaos from switched-capacitor circuits: Discrete maps

Abstract: A special-purpose analog computer made of switched-capacitor circuits is presented for analyzing chaos and bifurcation phenomena in nonlinear discrete dynamical systems modeled by discrete maps x n + 1 = f(x n ) Experimental results are given for four switched-capacitor circuits described by well-known discrete maps; namely, the logistic map, the piecewise-linear unimodal (one-hump) map, the Henon map, and the Lozi map.

The simulation of general circuits containing ideal switches

Abstract: Issues related to the design and use of a digital computer simulation of generai circuits containing ideal switching elements are presented. Problems due to circuit topology changes, methods of controlling the switching elements, techniques for studying transient, cyclic, steady-state, and small-signal frequency response behavior are considered.

Integrated switched-capacitor filter with improved frequency characteristics

Abstract: A switched-capacitor filter constituted in the form of a semiconductor integrated circuit has an input circuit which consists of at least one noninversion-type switched-capacitor and at least two inversion-type switched-capacitors that are connected in parallel with each other. The two inversion-type switched-capacitors have different writing timings and reading timings relative to each other. With this setup, capacitances of the switched-capacitors need not be extremely increased even when it is desired to maintain a zero-point frequency of the filter at a very low value. Further, there is no need of providing a circuit such as sample holding circuit which requires extra area and consumes additional electric power.

GaAs switched-capacitor circuits for high-speed signal processing

Abstract: Switched-capacitor building blocks are presented which are suitable for implementation in GaAs MESFET technology. They include gain stages, operational amplifiers, and transmission gates. Switched-capacitor design techniques are discussed that minimize filter sensitivity to GaAs op-amp limitations. Experimental results are presented on a variety of GaAs switched-capacitor circuits, including a gain stage, a second-order bandpass filter, and a third-order low-pass filter. The circuits demonstrate sampling rates exceeding 100 MHz without significant loss of accuracy.

Switched capacitor mixer/multiplier

Abstract: A sequence of samples of a time varying signal is multiplied by respective, corresponding, multiplicands corresponding to values of a separate signal. The multiplicands are provided as ratios of capacitances switched into and out of a circuit between the input time varying voltage and an accumulating integrator. The arrangement is used to provide multiplication of a time varying signal by corresponding amplitudes of a sinusoid without requiring generation of a sinusoid. The arrangement is used for sampling, detecting signals utilizing a simulated local oscillator signal, and for generation of an arbitrary time varying function.

Spike-free switched-capacitor circuits

Abstract: A novel circuit technique is presented to prevent op-amps in switched-capacitor circuits from generating ‘spikes’ in the nonoverlapping period of clock phases. This technique is universal in that it is applicable to offset-compensated, parasiticand gain-insensitive amplifiers, integrators and sample/hold circuits. Experimental waveforms are also given to demonstrate its validity.

Modeling charge injection in MOS analog switches

Abstract: Charge injection in MOS switches has been analyzed. The analysis has been extended to the general case of including source resistance and source capacitance. Universal plots of percentage channel charge injected are presented. Normalized variables are used to facilitate usage of the plots. A small-geometry switch, slow switching rate, and small source resistance can help reduce the charge injection effect.

A Low-Cost Multichannel Preamplifier for Physiological Signals

Abstract: A preamplifier for physiological signals (ECG, EMG, etc.) is described for general use in mnltichannel applications. The limited number of components made it possible to implement eight channels on one Eurocard printed circuit board (160 x 100 mm) and 64 channels in a 9.5 in cabinet in a cost-effective manner (about $ 50 per channel). The use of a monolithic instrumentation amplifier based on the current feedback principle resulted in high dc suppression combined with excellent noise performance and high common mode rejection. A second-order Butterworth low-pass filter was implemented using switched capacitor circuits, so that in a multichannel setup the rolloff frequency of all channels can be (digitally) controlled by one clock frequency.

Linearization of voltage-controlled oscillators using switched capacitor feedback

Abstract: The voltage-frequency characteristics of any voltage-controlled oscillator can be linearized using a simple circuit containing a switched capacitor The oscillation frequency becomes insensitive to power supply or temperature variations, and is determined only by the values of a capacitor, resistor, and the control voltage with respect to a reference voltage

Display line driver with automatic uniformity compensation

Abstract: An on-substrate driver circuit for a display line of a liquid crystal display having an amplifier connected in conjunction with an amplifier input capacitor, a sample/hold capacitor and three switches. The circuit operates in a first compensation mode wherein the first and second of the switches connect both a null reference voltage and the amplifier output voltage to the amplifier input capacitor, effectively nulling out or compensating for offset between the turn-on threshold, and hence the output, of a plurality of amplifiers on the display. After compensation, the circuit is switched to an operational mode wherein the first and second switches are open and a third switch connects the analog display signal to the sample/hold capacitor. A second preferred embodiment employing a double buffer including two consecutive, serially connected amplifier stages as described is also disclosed. In practice, a plurality of such double buffer circuits are arranged along the edge of a liquid crystal display panel and supplied with a common input signal by a single off-substrate input signal line.

A 3.6-MHz cutoff frequency CMOS elliptic low-pass switched-capacitor ladder filter for video communication

Abstract: The high frequency (HF) behavior of the switched-capacitor (SC) LDI ladder filter is studied. This study shows that using low sampling frequency with respect to the cutoff frequency reduces the HF error due to the reduction in amplifier gain. Design techniques are also given for the HF SC filters, such as double-sampling scheme, a low sampling frequency with an exact synthesis algorithm, as well as a fast-settling folded-cascode amplifier. These techniques are applied to an experimental fifth-order elliptic SC filter fabricated in a 2-/spl mu/m CMOS technology. The experimental results show that a 3.6-MHz cutoff frequency is attained. All the capacitors are scaled down in order to reduce the setting time of the amplifiers. The active area of the filter is 0.9 mm/SUP 2/. The F/SUB sampling//F/SUB cutoff/ is only 5. The circuit operates from /spl plusmn/5 V and typically dissipates 80 mW when sampled at 18 MHz.

A switched capacitor filter silicon compiler

Abstract: Switched capacitor technique is one of the best methods for making integrated HOS filters, A lot of programs are now available to help the designer but they are not connected to each other, and therefore a more general tool, taking into account all the design steps is needed.

Transient and Harmonic Voltages Associated with Automated Capacitor Switching on Distribution Systems

Abstract: One of the functions proposed for distribution automation systems is automated capacitor switching to control power factor and voltage profile on feeder circuits. This is one of the functions being implemented as part of the Athens Automation and Control Experiment on the Athens Utilities Board (AUB) in Athens, Tennessee. A concern with automated capacitor switching is the increase in harmonic and transient voltages due to different capacitor configurations on the distribution system. A study was performed to evaluate the impact of the automated capacitor switching on the AUB distribution system. The study has identified problem areas, methods for determining the problem areas, and possible solutions. The substation capacitor banks were found to be the dominant factor in both the transient and harmonic repsonses of the distribution system. The harmonic response of the system is dominated by the parallel inductance/capacitance of the circuit comprised of the substation capacitor and equivalent source reactance at the substation. The transient analyses indicated that when the substation capacitor is energized, magnified transient voltages can occur at switched-in feeder capacitors. An evaluation of the effect of automated capacitor switching is necessary to properly design the automated capacitor switching schemes and the required arrester protection for any harmonic and/or transient overvoltage contingency.

Design techniques for improved capacitor area efficiency in switched-capacitor biquads

Abstract: The capacitance ratio constraint for equal op-amp dynamic range is derived in this paper for a collection of important biquad configurations of all filter types. This completes the set of explicit design constraints for the determination of capacitance values. The relations between the total capacitance and design parameters such as \omega_{0}T, Q and peak gain are then transparent to the designer. Computer simulation is no longer a necessity for achieving optimal dynamic range for the biquad. By analyzing a design example of [1], three observations are made with regard to the capacitor area efficiency of a biquad. These observations help the designers to quickly determine the capacitor area efficiencies of available biquad configurations. Different techniques are proposed to improve the capacitor area efficiency of existing biquads. It is shown that simply rearranging the clock phases and input capacitors according to these observations can result in new configurations that improve the total capacitance significantly. Another technique proposed in this paper splits the integrating capacitor of a biquad for different clock phases. In doing so, capacitors unnecessarily linked up with big integrating capacitors can be sealed down and significant saving in total capacitance is achieved. Influence of this technique on the error due to op-amp gain being finite is discussed. Comparisons of the new techniques with the published examples show that 30 to 40-percent savings in total capacitance can be achieved.

Present and future applications of switched-capacitor circuits

Abstract: An overview of switched-capacitor (SC) circuit applications is presented. SC functional blocks, which play an important role in many systems, are discussed. Several large-scale integrated circuits, which are mainly for commercial use, are outlined, placing stress on why SC circuits are used. These include codecs, modems, and speech analysis and synthesis circuitry. Projected future SC circuit performance is discussed in comparison with digital signal processing technology. Promising application fields are identified.

Solid state watthour meter with switched-capacitor integration

Abstract: A switched-capacitor integrator is employed in an electronic watthour measurement device for integrating the average component of a product signal formed by pulse-width modulating an analog signal proportional to one of a load current and voltage at a pulse duty ratio proportional to the other of the load current and voltage. A hysteresis comparator forces the direction of integration to alternate between positive and negative limits for balancing out offset voltages in the integrator and comparator. A triangular-wave generator employed as part of the pulse-width-modulation technique is also implemented using a switched-capacitor integrator. The switched-capacitor integrators permit fabrication of the circuit with the required accuracy without needing external, discrete time-constant-determining resistances and capacitances. Measurement accuracy is determined by the ratio of capacitances of two on-chip capacitors, the accuracy to a clock signal and two reference voltages. These parameters are closely controllable on a single MOS or CMOS chip using normal process control whereby the entire electronic watthour measurement device may be realized on a single chip without requiring off-chip components.

DC to DC converter

Abstract: A DC to DC converter of the switched capacitor kind is described in which controlled solid state switches are used to effect the switching and to limit the current passed to the capacitors in dependence upon that required to match a load.

Switched capacitor arrangement

Abstract: An integrator of a Sigma-Delta modulator includes an amplifier having an inverting input terminal and an output terminal. AN integrating capacitor is coupled between the input and output terminals. An input signal is coupled via a switched capacitor arrangement to the input terminal. The switched capacitor arrangement includes first and second transmission gates, operating at a first frequency, and a second capacitance that are coupled in series. In each period of the operation of the transmission gates, the first transmission gate is turned off before the second transmission gate for preventing a charge injected by the second transmission gate when the second transmission gate is turned off from being coupled to the input terminal of the amplifier.

An autoranging switched-capacitor analog-to digital converter

Abstract: A novel switched-capacitor serial analog-to-digital (A/D) converter is developed based on the dual-slope integration. The analog voltage being converted is first accumulated into the capacitor in the form of charge. The quantized reference charge is then extracted from the accumulated signal charge until the voltage across the capacitor becomes zero. To increase the resolution, the autoranging function is incorporated which changes the charge accumulation count in 2's geometric progression manner according to the input analog voltage. The resultant counts in charge accumulation and extraction give the exponent and the mantissa, respectively, of the floating-point binary representation. A resolution of 10 bits with the additional $2{1 \over 2}$ bits for the exponent is achieved by the prototype converter built using discrete components.

A method for frequency-domain analysis of switched-capacitor filters

Abstract: In this paper, a new method is proposed for the frequencyresponse evaluations of switched-capacitor networks of any topology. It relies on reducing the z -transform impulse response of the SCN into a rational function form. Closed-form expressions for the coefficients of the rational expansion, as well as its degree, are given. Illustrative examples showing the merits of this new approach over the existing one .are also included.

The LUD approach to switched-capacitor filter design

Abstract: A new design method for switched-capacitor filters (SCF) is presented. It is based upon an LU matrix decomposition technique and has the distinct advantage of producing SC filter realizations containing no delay free loops. These are formed traditionally by capacitors and opamps in leapfrog realizations. It is demonstrated that this feature should render reduced dependence of the filter response to nonideal effects such as finite amplifier GB and switch resistance. Results from realistic leapfrog and LUD SC filter realizations confirm this.

A novel technique for the on-chip tuning of monolithic filters

Abstract: Monolithic analog filters, with the exception of switched capacitor filters need on-chip tuning. Existing schemes of PLL and master-slave techniques use phase control for tuning. The proposed method uses amplitude detection, where the reference voltage itself is derived from the input. Much work has recently been done on active RC continuous-time filters in VLSI [4]-[8]. The heart of all such systems is an integrator with a voltage-variable time-constant (VVI). To generate the control for the VVI, these schemes use either a self-tuning filter (follow the master technique) [5] or a phase-locked loop [8], locking on to a stable reference frequency. Unlike these techniques which are essentially phase-control schemes, what is proposed here is a gain-control scheme.