Showing papers on "Switched capacitor published in 1989"

Switched currents-a new technique for analog sampled-data signal processing

Abstract: A technique called 'switched currents,' for analog sampled-data signal processing in the current domain, is introduced. A family of modules that are capable of various computational and memory functions is described. The modules are well suited to system building as demonstrated by the simulation of a sixth-order Chebyshev low-pass filter. Circuit techniques that enhance analog performance are offered. >

MOS Switched-Capacitor and Continuous-Time Integrated Circuits and Systems: Analysis and Design

Abstract: Contents: Fundamentals of Sampled-Data Systems * MOS Devices for Linear Analog Integrated Circuits * Basic Properties and Systematic Analysis of Switched-Capacitor Networks * Basic Building Blocks of Linear SC Networks * Synthesis and Design of SC Filters * Design of Adaptive and Nonlinear Analog CMOS Circuits: Building Block Approach * CMOS Analog to Digital and Digital to Analog Conversion Systems * Subject Index.

Dummy transistor compensation of analog MOS switches

Abstract: Theoretical and experimental results of the clock-feedthrough phenomenon (charge injection) in sample-and-hold circuits using minimum features size transistors of a self-aligned 3 mu m CMOS technology are compared. The lumped RC model of the conductive channel is used and verified in different switch configurations with variable input voltages. Special emphasis is placed on the feasibility and limits of charge cancellation techniques using dummy switches. >

A parasitic-insensitive area-efficient approach to realizing very large time constants in switched-capacitor circuits

Abstract: A novel switched-capacitor technique for realizing very large time constants is presented. The technique is insensitive to parasitic capacitances and is very area-efficient. It does not require a complicated clocking scheme. The technique yields a complete family of integrators which in turn can be used to realize higher-order filtering functions based on cascaded biquadratic sections or ladder filters. These integrators have been used to implement an experimental 60-Hz notch filter working from a 128-kHz clock. >

Analysis and sensitivity of periodically switched linear networks

Abstract: A completely general computer-oriented method for exact frequency-domain analysis of multiphase periodically switched linear networks is presented. Input signals can be either continuous or sample-and-held. The theory is valid even for cases where the network variables are discontinuous during switching. An algorithm to compute sensitivity of the response to element changes is also given. The method unifies analysis of general switched linear networks and ideal switched capacitor networks to a single algorithm. Equation formulation is based on the two-graph modified nodal analysis. The theoretical results presented are compared to previously published results. The theories have been implemented in a computer program. Numerical results of the analysis of three networks are given. They show the usefulness of the program in the analysis and design of switched networks. >

Compensated capacitors for switched capacitor input of an analog-to-digital converter

Abstract: A semiconductor capacitor for use in an analog-to-digital converter includes two parallel connected capacitors with separate lower plates (44) and (46) fabricated of polycrystalline silicon and upper plates (52) and (54) also fabricated of polysilicon. The plates are separated by capacitive oxide dielectric structures (48) and (50). They are interconnected such that the lower plate (44) of one capacitor is connected to the upper plate (54) of the other capacitor and the lower plate (46) of the other capacitor is connected to the upper plate (52) of the first capacitor. With such a configuration, the odd ordered non-linearities contributing to the voltage coefficient errors are cancelled.

Method and apparatus for converting A/D nonlinearities to random noise

Abstract: A method and apparatus for removing the effects of mismatched components in an A/D converter is described. The present invention dynamically rearranges the capacitors of an A/D converter so that physical mismatch is averaged out. In the preferred embodiment of the present invention, an array of equally-sized capacitors is coupled to a switching network. A successive approximation scheme is implemented in which the input signal is coupled through SAR switches to the capacitor array. Each switch is coupled to 2 N-1 capacitors where N is the switch number. For example, in an 8-bit scheme, there are 3 switches with switch 1 coupled to one capacitor, switch 2 coupled to two capacitors, and switch 3 coupled to four capacitors. In this manner, eight levels of capacitance values can be defined. The present invention adds a scramble control code to control the switching array so that the physical capacitors themselves are coupled to different SAR switches at different times. This requires a scramble matrix of switches, which in the present invention requires N×2N switches where N equals the number of bits of control code. In this manner, the effects of any variations in the capacitance ratios is averaged out and converted to noise which can be filtered out of the signal.

A switched capacitor, inductorless DC to AC voltage step-up power converter

Abstract: A technique for efficiently producing low-harmonic, 60 Hz sinusoidal 110 V AC from a 24 V DC source without inductors or transformers is presented. The novel circuit topology allows the same power MOSFETs that sequentially charge a bank of capacitors to synthesize the staircase sine wave approximation. A Fourier analysis of the effects of MOSFET on-resistance and switching time on a 1 kW prototype is presented. >

Fourth order sigma-delta modulator circuit for digital audio and ISDN applications

Abstract: A fourth order switched capacitor sigma-delta modulator architecture is presented providing extremely high signal to quantization noise ratio with modest circuit level demands for digital audio specification. Tolerable nonidealities in subcircuits are specified by system level simulation. The subcircuits are designed to fulfil the digital audio specification. Five modulators are fabricated in order to investigate the 1/f-noise elimination. >

Bi-level ballast circuit for operating hid lamps

Abstract: A bi-level ballast network is disclosed for operating an HID lamp (16) at either a low power or standby level and at a high power or full light level. The network includes an unswitched capacitor (C1) connected to the transformer ballast coil and a switched capacitor (C2) connected to a solid state relay (SSR) circuit (26), the electronic components providing the switching therein being back-to-back SCR's (23, 25). When the SSR (26) is operated switch contacts (24, 28) connected to the switched capacitor (C2) open or close at the next subsequent zero crossing of the applied ac source voltage. This changes the capacitance of the network to increase the power to the lamp or decrease the power thereto depending on the operating conditions prior to the SSR (26) being operated. Current, voltage and dvdt protection devices (22, 36, 38) are also provided.

Circuit for shaping and making use of armature current ripple as generated by a D.C. motor, in particular for position control

Abstract: The present invention provides a circuit for shaping ripple in the armature current of a D.C. motor. The circuit includes a phase-locked loop (100). In addition, the circuit preferably includes a back-e.m.f. circuit (300) suitable for generating a signal proportional to the back-e.m.f. of the motor and for controlling the frequency of the phase-locked loop (100) on the basis of the signal obtained in this way and/or the back-e.m.f. circuit (300) suitable for generating a signal proportional to the back-e.m.f. of the motor, a voltage controlled oscillator (500) controlled by the signal proportional to the back-e.m.f., and a switched capacitor filter (400) controlled by the output of the oscillator (500), the filter being connected upstream from the phase-locked loop (100).

Consistent initial conditions of linear switched networks

Abstract: A method for obtaining consistent initial conditions of linear switched networks is presented. The major difficulty in the analysis is the discontinuity of network variables and the presence of impulsive voltages and currents at the switching instants. The method entails a two-step integration based on a special numerical Laplace inversion. It is applicable to any linear circuit configuration; capacitor loops, inductor cutsets, ideal switches with zero impedance or admittance, and impulsive sources do not present problems. An important application is in computing the switching transformation matrices that relate the initial conditions of the network to the circuit conditions before switching. These matrices are needed in frequency analysis of general periodically switched linear networks. The algorithms have been implemented and tested in a computer program WATSNAP. >

Switched-capacitor filters

Abstract: A novel technique for building active filters using switched-capacitor (SC) circuits is proposed. The principle of operation, methods of control, and analysis and design of a typical SC filter are presented. To assess its effectiveness, the technique is used to control input current harmonics in a phase-controlled converter. It is shown that by using a single filter a wide range of harmonics can be controlled. >

Digital-to-analog converter using switched capacitor and transverse filter

Abstract: The converter incorporates a transversal filter. The filter delays are implemented in digital form prior to conversion into analog signals (preferably using switched capacitor techniques). One form of switched capacitor converter (with or without filtering) employs a single capacitor, common to a plurality of bits, appropriate weighting of the bits being achieved by controlling the switching.

Switched-capacitor analog-to-digital converter with autocalibration

Abstract: The present invention provides a switched capacitor analog-to-digital converter (6) for the sampling of an analog input signal and conversion to an equivalent digital format utilizing a multi-slope conversion technique. The elements comprising the converter are, preferably, integrated onto a single chip using CMOS technology. The converter (6) includes a processor (14) for coordinating switching in the converter and generating the digital output signal. A sampling circuit (15) having a switched capacitor (16) controlled by the processor (14) is included in the converter for sampling the voltage of the analog input signal and transferring charge representative of the analog input signal between an integrator (20) and the sampling circuit (15). Further included in the converter is a discharge circuit (36) for either transferring charge to the integrator (20) or receiving charge from the integrator (20). The discharge circuit (36) is comprised of a number of switched capacitors (38a-38f) having capacitances that are powers of two relative to one another to provide binary-weighted transfers between the discharge circuit (36) and the integrator (20). Further, the processor (14) can control, by using the switches (24, 40a-40f), the direction of charge transfer using a single reference voltage (VR). Further, the converter (6) provides an autocalibration feature which compensates for deviation in the binary ratio of capacitances of the switched capacitors (38a-38f) employed in the discharge circuit (36).

New monolithic switched-capacitor differentiators with good noise rejection

Abstract: Inverting and noninverting switched-capacitor (SC) differentiators suitable for integrated-circuit implementation are proposed and analyzed. Their structures are simple, parasitic-free, and less sensitive to offset voltage and power-supply voltage changes. In addition, their fabrication process and operating clocks are fully compatible with conventional SC integrators. Noise analysis shows a good low-frequency noise-rejection capability. The high-frequency noise can be suppressed and does not overdrive the output of the SC differentiators. To demonstrate the application of the SC differentiators in the SC filter, a bandpass differentiator-type biquad is presented. Both the differentiators and the biquad have been fabricated and measured. The differentiation waveforms and the good consistency between the measured and the simulated circuit responses verify the correct operation of the SC differentiators. >

A switched-capacitor interface for capacitive sensors with wide dynamic range

Abstract: A novel switched-capacitor interface for capacitive sensors has been developed based on a dual-slope analog-to-digital (A/D) conversion technique. The interface consists of a switched-capacitor integrator, a comparator, and digital circuits. The integrator first samples the sensor capacitance in the form of its proportional charge. A quantized reference charge is then extracted until the output voltage of the integrator becomes zero. An autoranging function is incorporated to achieve a wide dynamic range of sensor capacitance by changing the sampling count in a 2's geometric manner. A prototype interface built using discrete components has demonstrated a capacitance measurement over four decades with an accuracy better than 1%. >

Implantable cardiac defibrillator employing a switched capacitor gain/filter stage having a transient-free gain change

Abstract: An implantable cardiac defibrillator includes electrodes coupled to a patient's heart, sensing circuitry having inputs connected to the electrodes for sensing cardiac electrical signals, charging means for storing a charge, and discharge means for delivering a shock to the heart. The sensing circuitry includes switched capacitor gain/filter means for providing an output signal which is transient-free during a gain change operation and which maintains a constant filter bandwidth for each gain setting.

Switched capacitor differentiators and switched capacitor differentiator-based filters

Abstract: Backward-mapping switched capacitor (SC) differentiators for MOS technology integrated circuit implementation, as well as forward mapping (FM) and bilinear-mapping (BIM) SC differentiators, are disclosed. The SC differentiator is employed in filters either alone or in combination with SC integrators. The filters include biquads, ladder filters, FIR filters, IIR filters and N-path filters. A fully differential operational amplifier with high and symmetrical driving capability is also described.

Switched capacitor amplifier circuit

Abstract: A switched capacitor amplifier circuit using a pair (C1, C3) (C2C4) of switched capacitors to replace each resistor element of an inverting operational amplifier circuit (12), with the capacitors operating on opposite halves of the switching cycle to provide reduced sampling distortion.

A 2.4 amu;m CMOS switched-capacitor video decimator with sampling rate reduction from 40.5 MHz to 13.5 MHz

Abstract: A description is given of the design and integrated-circuit implementation of a fifth-order elliptic lowpass switched-capacitor (SC) video decimator with a cutoff frequency of 3.6 MHz and sampling rate reduction from 40.5 MHz to 13.5 MHz. A recently proposed decimator architecture used to make the settling time requirements of the operational amplifiers similar to those of a conventional SC filter with switching frequency of only 13.5 MHz. The circuit is implemented using a 2.4-mm CMOS double-poly process yielding a total area of less than 1 mm2. The power consumption is less than 50 mW with a 10-V power supply

Switched-capacitor DFT and IDFT circuit

Abstract: The switched-capacitor realization of the discrete Fourier transform (DFT) is treated in this paper as well as the inverse discrete Fourier transform (1DFT). The output of the DFT has a sinusoidal waveform including the amplitude and phase information of the required spectra. These spectra are given simultaneously and almost in real time. The output of the 1DFT is given merely by adding DFT outputs. Furthermore, the circuit configuration of this system-from input to DFT, from DFT to 1DFT, and from 1DFT to output-is a very simple configuration constructed by a non-recursive filter circuit.

A time-multiplexed switched-capacitor circuit for neural network applications

Abstract: A time-multiplexed switched-capacitor computational block with some neural network characteristics is under development. The goal of this work is not to model biological neuron qualities exactly but rather to emulate their primary characteristics to the extent necessary to solve some types of problems not suited to digital processing. The circuit operation and limitations on its performance are described. The circuit is intended to serve as a coprocessor to a digital microprocessor. Circuit functionality has been demonstrated with breadboarded circuit, and the circuit is currently being integrated. >

An acoustic charge transport digitally programmable transversal filter

Abstract: A monolithic 64-tap digitally programmable analog transversal filter is described that uses an acoustic charge transport (ACT) tapped delay line and integrated GaAs MESFET circuits for coefficient storage and tap weight circuitry. The device has 6-b tap weights, an input sampling rate of 360 MHz, and an output tap spacing corresponding to an output sampling rate of 130 MHz. This results in the effective execution of 8*10/sup 9/ multiply and sum operations per second in a 38-mm/sup 2/ chip that dissipates less than 2 W. This effective computational rate is limited in the present design by the spacing of the ACT delay line taps, which is dictated by the geometry of the tap weight circuits. The chip uses fully random-access tap weight memory, which is easier to interface to typical digital controllers than the usual shift-register storage approach. Tap address and tap weight data are applied as parallel 6-b words, and the data work is clocked into the address location by the application of an enable pulse. The tap weight circuits use monolithic capacitors and GaAs MESFET analog switches to realize a multiplying converter based on a C/2C ladder configuration with a sign-and-magnitude tap weight word format. A ladder accuracy of 7 b is achieved by compensating the ladder component values for parasitics. >

Continuous-time and switched capacitor monolithic filters based on current and charge simulation

Abstract: The authors are concerned primarily with low-pass filters. A typical section on an LCR network for polynomial low-pass filters, which are those not possessing transmission zeros at finite frequencies, is presented. For this kind of filter, a signal-flow-graph (SFG) representation may conveniently be obtained. The authors choose as variables for the SFG the inductor currents and capacitor voltages and hence obtain the SFG presented. It is noted that the branch weights in the SFG are either +1 or -1 unity branches or are of the integrator form 1/sTi, where Ti is the value of an inductor or capacitor in the LCR network and s is the complex frequency variable. The authors combine the +1 and -1 branches, which occur in pairs, at the inputs or outputs of the 1/s type integrator branches, obtaining an implementation in terms of differential input integrators. The authors show that the use of current or charge integrators allows them to carry out nodal voltage scaling while at the same time obtaining low sensitivity which is not possible using voltage integrators alone. For elliptic filters, use of a judicious combination of voltages and currents (or charges) provides the lowest sensitivity of any approach with acceptable component parameter spread. >

A CMOS voltage-controlled linear resistor with wide dynamic range

Abstract: A type of voltage-controlled linear resistor utilizing a simple combination of complementary enhancement mode MOS transistors is proposed. The design is suitable not only for discrete use but also for use as a unit cell in integrated circuits. The electronic structure and the layout of the circuit are given. The principle of operation is discussed and is verified by computer simulation (using the program PSPICE). Parameters for practical design have been established, with satisfactory agreement with simulation results. >

Implantable cardiac defibrillator employing a switched capacitor stage having a non-50/50 duty cycle

Abstract: An implantable cardiac defibrillator employing a switched capacitor stage wherein the switches are clocked in a non-50%/50% ratio such that an operational amplifier has greater than 50% of the clock period to acquire the desired voltage and less than 50% of the clock period to hold the acquired voltage, thereby allowing the circuit to run at an overall lower current drain.

Micropower analog structures for a CMOS heart rate indicator

Abstract: A micropower heart-rate indicator integrated with CMOS technology and using several micropower blocks is currently under development. So far the complete DC-compensated preamplifier and the switched capacitor (SC) filter have been designed and tested. The designs of these structures and measurement results are presented. The SC filter consists of several sections, including an input decimator, lowpass filter, decimation/SH section, and highpass filter. Filter performance was measured by varying the temperature, supply voltage, and bias current. The temperature effects were minor, but any reduction in the GBW of the operational amplifiers with reduced bias current caused marked variations in the results. In addition, any reduction in the supply voltage below +or-1 V caused an abrupt attenuation of the amplitude response of the filter as the on-resistance of the CMOS switches increased due to inadequate clock amplitude. >

CMOS readout electronics for operation at cryogenic temperatures

Abstract: A readout electronics for a liquid-argon calorimeter is discussed. It is designed and optimized for operation at cryogenic temperatures and it is integrated in an n-well 2- mu m CMOS technology. The chip contains 16 analog channels with switched-capacitor circuits for charge collection, storage, and amplification, and averaging and correlated double-sampling circuits for noise reduction. Further components include a trigger generator, an analog multiplexer, digital control circuits for analog switching, and 50 ohm cable drivers. >