Showing papers on "Switched capacitor published in 1993"

Analogue IC design : the current-mode approach

Abstract: * Chapter 1: Introduction * Chapter 2: Current-mode Circuits From A Translinear Viewpoint: A Tutorial * Chapter 3: Current Conveyor Theory And Practice * Chapter 4: Universal Current-Mode Analogue Amplifiers * Chapter 5: High Frequency CMOS Transconductors * Chapter 6: Bipolar Current Mirrors * Chapter 7: Dynamic Current Mirrors * Chapter 8: Gallium Arsenide Analogue Integrated Circuit Design Techniques * Chapter 9: Continuous-Time Filters * Chapter 10: Continuous-time and Switched Capacitor Monolithic Filters Based on LCR Filter Simulation using Current and Charge Variables * Chapter 11: Switched-Current Filters * Chapter 12: Analog Interface Circuits For VLSI * Chapter 13: Current Mode A/D and D/A Converters * Chapter 14: Applications of current-copier circuits * Chapter 15: Integrated Current Conveyor * Chapter 16: Applying 'Current Feedback' to Voltage Amplifiers * Chapter 17: Neural Network Building Blocks for Analog MOS VLSI * Chapter 18: Future of Analogue Integrated Circuit Design

Use of ESR for deterioration diagnosis of electrolytic capacitor

Abstract: A new deterioration diagnosis method for the electrolytic capacitor is proposed for a forward-type converter and a buck-boost converter. It was observed that the ESR (equivalent series resistance) of the electrolytic capacitor increases as it deteriorates, and the knowledge that ripple varies proportionally to the ESR increase was used. With this method, the electrolytic capacitor life-cycle aging rate can be projected for the active circuit over the system life. This approach to deterioration is valid for any load condition, no matter whether the circuit has feedback control or not. >

An 8-b 85-MS/s parallel pipeline A/D converter in 1- mu m CMOS

Abstract: A new architecture consisting of a time-interleaved array of pipelined analog-to-digital converters (ADCs) is presented. A prototype has been designed consisting of four switched-capacitor (S/C) multistage pipelined ADCs in parallel. Hardware cost is minimized by sharing resistor strings, bias circuitry and clock generation circuitry over the array. Digital error correction is employed to ease comparator accuracy requirements. Techniques are employed to minimize the effect of mismatches across the array. A key circuit issue is the design of a high-speed sample-and-hold (S/H) amplifier: a fully differential, mostly NMOS, non-folded-cascode operational-amplifier topology is used. An experimental chip was implemented in 1- mu m CMOS and 8-b resolution at a sample rate of 85 megasamples per second (MS/s) was obtained. Signal-to-noise plus distortion (S/(N+D)) was 41 dB for an input sinusoid of 40 MHz. >

A novel readout chip for silicon strip detectors with analog pipeline and digitally controlled analog signal processing

Abstract: A readout chip for silicon strip detectors with analog event pipeline has been fabricated (SACMOS 2 μm technology) and tested. The chip has been designed to operate at the HERA ep collider at a bunch crossing rate of 10.4 MHz. Each channel has a layout width of 44 μm and consists of a fast, low noise, low power preamplifier followed by a switched capacitor analog event pipeline. The preamplifier consists of a single CMOS push-pull gain cell and offers minimal power consumption. A novel feature of our chip is a self-reading architecture that allows the preamplifier to re-read its own pipeline buffers and thus permits a extensive parallel analog signal processing that is digitally controlled. The results from radiation damage tests with 60 Co are given for doses up to 240 krad.

Continuously regulated series capacitor

Abstract: A new method for the continuous regulation of series reactive power compensation is presented. The two control circuits proposed consist of capacitor banks inserted in a transmission line and are controlled by bidirectional gate turn-off switches. The level of compensation is controlled by varying the on and off time of the GTO switch. To avoid current surges the switch is turned on before the capacitor voltage is zero. The feasibility of this method is verified by transient analysis and by measurements on a small-scale model. The advantage of the proposed method is the fast and continuous regulation of series compensation. A circuit can be built with available components and can be used for impedance control and oscillation reduction. >

TOSCA: a simulator for switched-capacitor noise-shaping A/D converters

Abstract: A software tool named TOSCA (Tool for Oversampled Switched-Capacitor A/D Converter Analysis) is described. The simulator is behavioral, general purpose and fully user-friendly. Because a set of basic building blocks is available, generic switched-capacitor noise-shaping A/D converters can be analyzed simply by building netlist file. Two hierarchical levels have been considered for circuit description: block level for subcircuits like quantizers and digital filters, and component level for subcircuits like the integrators where switches, capacitors and operational amplifiers are used as building elements. The developed models allow the most relevant nonideal parameters of the components to be taken into account, and a set of postprocessing facilities allows extensive analysis of the circuits. The program is written in C language, uses dynamic memory allocation, and is very fast. >

Testable switched-capacitor filters

Abstract: A design-for-testability (DFT) methodology for switched-capacitor (SC) filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off- and online test. A programmable biquad is used for on-chip comparison of the transfer functions for every filter stage. Test area overhead consists of the programmable biquad, a set of switches, and a finite-sequential-machine (FSM) control part. The design and implementation of an example filter are included to assess the potential usefulness of this approach. >

Switched capacitor D/A converter

Abstract: A set of N digital data bits serially supplied to an input node are converted to an analog voltage by means of N binary weighted capacitors and N switching transistors, one capacitor being associated with one switching transistor for each one of the N digital data bits. Each capacitor is connected between an output node and via the conduction path of its associated switching transistor to a first power terminal. Two transistors are used to selectively sample the N bits of serial data and to couple and store the sampled data on the gates of the switching transistors which are precharged so that the two transistors coupling the serial data only need to conduct in the common source mode. The serial data applied to the gates of the switching transistor is transferred to the N capacitors when a charging voltage is applied to the output node. Following the data transfer onto the binary weighted capacitors, the switching transistors are precharged and, concurrently the N capacitors are connected in parallel to produce an analog voltage corresponding to the serial data.

Switched capacitor one-bit digital-to-analog converter

Abstract: A switched capacitor one-bit digital-to-analog converter is preferably utilized in the feedback path of a sigma delta modulator. The one-bit digital-to-analog converter includes first and second capacitors, a first switching circuit for coupling charge from a reference source to the capacitors, and a second switching circuit for coupling charge from the capacitors to positive and negative outputs, such as the summing junction of an operational amplifier. The switches in the second switching circuit have a cross-coupled configuration and are controlled by data dependent control signals. The data dependent control signals are structured such that charge is coupled from the capacitors to the summing junction on both clock phases, regardless of the state of the data. As a result, the sizes of the capacitors can be reduced by a factor of two for the same charge transfer.

One-bit switched-capacitor D/A circuit with continuous time linearity

Abstract: A modified lossy integrator digital-to-analog converter includes an amplifier (46) that receives an input on a summing node (48) and provides an output on a node (52). A feedback capacitor (50) is disposed across the input and output and has an output switched-capacitor (54) disposed in parallel therewith to passively distribute the charge thereacross. Switches (60) and (66) are operable to control the switching operation of the capacitor (54). Two input switched capacitors (70) and (94) are controlled by associated switches to switch charge onto the summing node (48) in a first clock cycle φ 2 . A one-bit data stream modulates the operation such that either the charge from the capacitor (78) is dumped onto the summing node (48) or the charge from the capacitor (94) is dumped onto the summing node (48). This operation during the φ 2 cycle provides an integrated output that is slew-limited. The full charge of the selected capacitor (78) or (94) is allowed to be completely dumped onto the node (48) prior to the output switched capacitor (54) being disposed across the feedback capacitor (50). This allows for a linear operation in this range. Thereafter, the charge is passively distributed across the feedback capacitor (50) in a linear fashion associated with the lossy integrator. This provides a conversion from a digital signal one-bit data stream to a continuous time output analog signal.

Biquadratic transconductance switched-capacitor filters

Abstract: A new type of sampled data filter consisting of transconductance elements, switches and capacitors, and called a transconductor switched-capacitor (TSC) filter is presented. Transconductance elements do not degrade their performance within a wide frequency range and tunable ones are available. The synthesis of TSC filters is explained on the basis of a signal flow graph realizing the general z-domain biquadratic transfer function. The transconductance elements employed as active devices are readily available in various technologies and are easily implemented and more suitable than operational amplifiers in a CMOS technology. Because the building blocks are not involved in any continuous feedback, frequency compensation is not necessary for stability purposes. The filter coefficients are determined by the clock pulse width and the transconductances, both of which can be tuned, and the integrator capacitors. This method can be easily generalized to the higher order filters. >

Switched-Opamp, a Technique for Realising full CMOS Switched-Capacitor Filters at Very Low Voltages

Abstract: Existing design techniques for very low voltage (1.5 V) switched-capacitor filters need the on-chip generation of clock-signals with a higher voltage to drive the MOS-switches. Here a novel technique for the realisation of low voltage switched-capacitor filters in CMOS technologies is introduced which uses clock signals with voltages equal to the power supply. This new technique is called switched-opamp because it replaces some critical switches in a classic biquad structure by opamps which are turned on and off. A 2nd order lowpass switched-capacitor filter has been implemented and is discussed. This filter operates at only 1.5 V power supply and has a total harmonic distortion of ?60 dB with a signal swing of 550 mV ptp . It is realised in a 2.4 ?m CMOS process with V T = ±0.9 V.

Adaptive switched-capacitor filters based on the LMS algorithm

Abstract: The implementation of adaptive FIR filters based on the LMS algorithm using SC circuits is described. Basically, the filters consist of a delay element, a summing circuit, an integrator, and a multiplier. The influence of nonideal effects of SC networks on the behavior of a given filter is investigated. It is shown that the nonidealities in the FIR filter part of the circuit can be eliminated by an additional constant tap element, whereas the main error source in the adaptation part is the multiplier- and integrator offset-errors. The errors can be compensated for using special offset-free circuits. Using the proposed offset-compensation schemes, the accuracy of a switched-capacitor adaptive filter is mainly determined by the nonlinearity errors of the multipliers. >

Error reduction in switched capacitor digital-to-analog converter systems by balanced sampling

Abstract: A switched-capacitor DAC system includes two switched-capacitor DACs and a load circuit. The switched-capacitor filter of the first DAC samples a reference voltage source, which produces a reference voltage, at a first rate and the switched-capacitor filter of the second DAC samples the reference voltage source at a second rate, greater than the first rate. The load circuit samples the reference voltage source at a rate such that the level of the reference voltage is the same each time a sample is taken. The load circuit effectively equates the sampling of the two filters and substantially eliminates problems related to gain errors and low frequency quantization noise.

An integrated sensor for invasive blood-velocity measurement

Abstract: Invasive measurements of physical parameters in blood are very important for the intensive care. The integrated flow sensor presented here has been developed as a part of an ‘intelligent catheter’ for measuring certain blood parameters. The sensor is based on the principle of hot-film anemometry. The temperature difference on a chip is measured by two diodes. One diode is heated by means of a polysilicon resistor in close proximity. This diode is (for thermal insulation) placed on a 5 μm × 260 μm × 260 μm silicon membrane. For the membrane formation the implanted oxide layer of SIMOX substrates ( S eparation by Im planted Ox ygen) was used as a stop for backside etching. This technique allows batch processing and is compatible with a standard CMOS process. In addition, electronic CMOS devices can be mounted directly into the membrane. Switched capacitor circuits are used for sensor read-out electronics. The differential voltage at the diodes is amplified by means of a two-stage operational amplifier with an overall amplification of 238. The total chip size amounts to 1 mm × 5 mm. A change of flow velocity from 0 to 80 cm/s results in a change of the pulse width of 20 μs for a maximal chip temperature of 13 K relative to the ambient.

Improving the testability of switched-capacitor filters

Abstract: A design-for-test methodology for SC filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off- and on-line tests. The approach uses a comparison (voting) mechanism to indicate whether or not two copies of a filter element (a biquad, for instance) have a similar response during their actual operation. The design and implementation of a few filter examples are included to assess the potential usefulness of this new approach.

Optical power conversion

Abstract: An optical power conversion circuit converts an optical energy signal from an optical source, such as a laser diode, to a regulated D.C. electrical voltage using a single photodetector. A buck-boost circuit uses electrical current from the photodetector in response to the optical energy signal to store energy in an inductor during one polarity of a control signal, and transfers the energy from the inductor to an output capacitor during the other polarity of the control signal. The duty cycle of the control signal determines the regulated D.C. electrical voltage. A switch drive circuit generates the control signal as a pulse width modulated signal from the regulated D.C. electrical voltage and a reference voltage. The control signal is A.C. coupled to a pair of FET switches in the buck-boost circuit to alternately energize and charge the inductor and capacitor respectively. A switched capacitor is coupled in parallel with the photodetector to store energy from the photodetector when the inductor is transferring energy to the output capacitor. At startup one of the FET switches in the buck-boost circuit is normally closed and the other normally open, and a third FET switch decouples the switched capacitor from the photodetector. A startup modulation signal is generated at the optical source to provide switching action equivalent to that of the FET switches in the buck-boost circuit until the regulated D.C. voltage achieves a sufficient level to energize the switch drive circuit and sustain normal operation. A data pickoff circuit is inserted in series with the photodetector to retrieve a data signal impressed upon the optical energy signal without disturbing the D.C. content.

Active filter circuit suited to integration on IC chip

Abstract: An active filter circuit has been proposed which is fabricated on a chip and which comprises a two-input operational amplifier with one input for feedback, and a first capacitance element connected between the other input of the operational amplifier and the ground potential. It further comprises a main resistor and the supplemental resistors interconnected in series or parallel, and switches corresponding to the supplemental resistors and turned on or off by control signals, thereby the summed resistance of these supplemental resistors is adjustable to set the time constant created in combination with the capacitance of the first capacitor to a specified value. Input signals are routed to the other input of the operational amplifier via the resistor circuit consisting of the main and supplemental resistors and the switches. According to the present invention, the time constant is detected with a probe pulse by measuring discharge time of the second capacitor. According to the detection results, the control signals are outputted to correct the deviation of the time constant from the specified value.

Charge-balanced switched-capacitor circuit and amplifier circuit using same

Abstract: A charge-balanced switched-capacitor circuit (50, 61) includes two capacitors (53, 54/72, 73) which are equalized by being connected in parallel during a first time period. This equalization cancels any mismatch in either capacitor (53, 54/72, 73) which would tend to affect an associated common-mode voltage. During a second time period, the two capacitors (53, 54/72, 73) are connected in series between two signal lines (42, 43). In one embodiment, the switched-capacitor circuit (50) forms a common-mode feedback sensing circuit by providing a common-mode feedback voltage to a fully-differential amplifier (41) at a common interconnection point of the two capacitors (53, 54). This embodiment draws no DC current, and thus prevents harmonic distortion of an output signal on the two signal lines when using a slew-rate limited amplifier (41). In another embodiment, the switched-capacitor circuit (61) functions as an input sampler at an input of a switched-capacitor amplifier circuit (60).

Glitchless switched-capacitor biquad low pass filter

Abstract: A fully differential switched-capacitor biquad low pass filter (40) includes a first stage (54), second stage (56), common-mode circuits (55, 72), and feedback transmission gates (73, 74). The first stage (54) includes a first operational amplifier (47), and the second stage (56) includes a second operational amplifier (69). Glitches, or transients, which are caused by the operational amplifiers (47, 69) operating in slew rate limit mode, are prevented from affecting the differential output signals of the filter (40) when the filter (40) is operating with a continuous time output. This is accomplished by preventing the operational amplifiers (47, 69) from operating in slew rate limit mode, or by adjusting the clock signals such that the output of the filter (40) is not coupled to an operational amplifier (47, 69) that is recovering from operation in slew rate limit mode.

Switched-capacitor chaotic neuron for chaotic neural networks

Abstract: A switched capacitor implementation of a neuron model which exhibits chaotic behavior is presented. The model is based on the experimentally observed characteristics of a squid neuron. It is shown that the proposed circuit qualitatively replicates the response of the real neuron by extensive simulations using SWITCAP2 and simulated program with IC emphasis (SPICE). Various nonideal effects such as DC gain, input offset voltage, and parasitic capacitances associated with SC implementation are investigated and the operational amplifier offset voltage is identified as a major problem. An existing offset voltage compensation scheme is adopted to alleviate the problem. >

An optimum CMOS switched-capacitor antialiasing decimating filter

Abstract: An optimum switched-capacitor (SC) decimating filter is capable of achieving a high input sampling frequency while the time period for the setting of the operational amplifiers can be maximized with respect to the lower output sampling frequency. Thus, for the same speed of the operational amplifiers, the oversampling ratio of the input signal in optimum SC decimating filters is much larger than in conventional SC filtering circuits, yielding a significant relaxation of the continuous-time prefiltering requirements. This is demonstrated by considering the design of a second-order SC antialiasing decimating filter with a threefold sampling rate reduction, which has been realized in a 1.8- mu m CMOS double-poly technology. The experimental evaluation of prototype samples confirms the expected operation of the circuit. >

54MHz switched-capacitor video channel equaliser

Abstract: A video channel equaliser consisting of a 54MHz switched-capacitor highpass filter in cascade with a continuous-time 15MHz lowpass postfilter has been implemented in 0.8μm CMOS. The equaliser has a three bit HF-gain control and serves as front end for a teletext data slicer.

Methods for adjusting the coupling capacitor of a multi-stage weighted capacitor A/D converter

Abstract: A circuit for adjusting capacitors in a capacitor analog to digital converter has a main capacitor array including more than one capacitor array portion 20 and 22, and at least one first coupling capacitor Cc. A first plate of each first coupling capacitor Cc is coupled to one capacitor array portion 22 and a second plate of each first coupling capacitor Cc is coupled to a next more significant capacitor array portion 20 such that each capacitor array portion is coupled to the next more significant capacitor array portion by one of the first coupling capacitors Cc. The circuit has at least one second coupling capacitor Cc3 with a first plate of each second coupling capacitor Cc3 coupled to the first plate of a corresponding one of the first coupling capacitors Cc. The circuit also has at least one array of calibration capacitors 60-84 with first plates of each array of calibration capacitors 60-84 coupled to a second plate of a corresponding one of the second coupling capacitors Cc3 and second plates of each array of calibration capacitors 60-84 coupled to corresponding switches 100-124. Switch control signals Sc4, Sc3, Sc2, Sc1, and Sc0, and S4, S3, S2, S1, and S0 control the switches such that each switch connects the corresponding calibration capacitor to either a first node Vref+ or a second node Vref-. Each switch control signal consists of two switch control bits which are combined by a logic function.

Digital cancellation of noise and offset for capacitive sensors

Abstract: A digital noise and offset cancellation technique for use with charge-redistribution capacitance sense techniques is presented. It is insensitive to parasitic capacitances, and can cancel the effects of offsets, low-frequency noise sources, and sampled kT/C noise of the MOS switch used in the topology. It represents a significant improvement in capacitance resolution than previous methods. It is currently being used in the readout circuits of experimental pressure sensor chips containing 100 fF air-gap capacitors with a resolution in the 30 aF range at a sampling speed of 11 kHz. >

A fuzzy controller using switched-capacitor techniques

Abstract: The use of switched-capacitor (SC) techniques to build a fuzzy controller is discussed. This is carried out at two levels: architecture, and cell design. Using a sequential architecture, the required building blocks are introduced and its realization is described. An advantage of this approach is the compatibility with sound analog techniques that can help in the design of the defuzzifier. The proposed system can be considered as a starting point for exploring the capabilities offered by SC networks for the hardware implementation of future fuzzy systems. >

Switched capacitor current reference

Abstract: A current reference using a switched capacitor to produce a substantially temperature invariant output current. Charge subtracted from a relatively large capacitor by a much smaller switched capacitor at a chosen rate substantially determines the output current of the reference. The output current is proportional to the product of a reference voltage, the capacitance of the switched capacitor and the switching frequency.

Switched-capacitor network

Abstract: Switched-capacitor network, having a switching device (S1, S1' to S16, S16'; Sk1, Sk1' to Sk12, Sk12') which alternately charges two first capacitors (C11, C11', C21, C21') of the same capacitance from a signal voltage source (+E, -E), which has opposite polarity to a reference potential (M), and subsequently discharges them via a respective input circuit of a differential amplifier (OP1, OP2), and which switching device, in synchronism with this, alternately charges in each case two second capacitors (C12, C12', C22, C22') of the same capacitance and in antiphase to one another from a reference voltage source (V1, V2), which has the same polarity as the reference potential (M), and subsequently discharges them via a respective input circuit of the differential amplifier (OP1, OP2). The switched-capacitor network also has two third capacitors (Cr12, Cr12', Cr22, Cr22') of the same capacitance as the second capacitors (C12, C12', C22, C22'), which third capacitors are charged by the switching configuration (S1, S1' to S16, S16'; Sk1, Sk1' to Sk12, sk12') in antiphase to the respective corresponding second capacitor (C12, C12'; C22, C22') from the reference voltage source (V1, V2), which has the same polarity as the reference potential (M), and are subsequently discharged via a respective input circuit of the differential amplifier (OP1, OP2).

A switched-capacitor delta-sigma modulator with reduced sensitivity to op-amp gain

Abstract: Low operational amplifier (op-amp) gain can degrade the performance of a switched-capacitor delta-sigma modulator ( Delta Sigma M). A Delta Sigma M that incorporates a new gain-compensated switched-capacitor integrator is described. The resulting Delta Sigma M topology has reduced sensitivity to op-amp gain. Simulation and measurement results for an experimental Delta Sigma M that demonstrate the advantages of the new architecture are presented. >

Offset-insensitive switched-capacitor gain stage

Abstract: An IC chip formed with an analog-to-digital converter having a switched-capacitor programmable gain stage and employing a switched-capacitor sigma-delta modulator. The chip includes pins to receive a number of different audio input signals which are selectively connectible to buffer amplifiers the outputs of which are directed to a switch to select one output for further processing. The selected buffer amplifier output is d-c coupled to an input signal terminal of a switched-capacitor programmable gain stage. The output of this gain stage is coupled to an output stage including an op-amp and associated switched-capacitor circuitry. The programmable gain stage has a reference input terminal which is connected through an IC chip pin to an external capacitor the other electrode of which is returned to signal common. This capacitor develops a d-c voltage corresponding to the offset voltages of the operative buffer amplifier and the op-amp, and including a component corresponding to charge-injection from MOS switches. Absorption of such d-c voltages by this capacitor prevents those voltages from being significantly gained by the amplifier circuitry, and thereby prevents those voltages from using up an excessive portion of the dynamic range of the circuitry.