Showing papers on "Switched capacitor published in 1994"

Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages

Abstract: The implementation of analog CMOS circuits that operate in the very low power supply voltage range (1 V to 2 V) becomes more important nowadays. Most accurate filter circuits are designed in the switched-capacitor technique. The existing design techniques require, however, the on-chip generation of a higher voltage by means of a voltage multiplier. In this paper, a novel technique, derived from the standard switched-capacitor technique, is presented. It is called switched-opamp because it is based on the replacement of the critical switches with opamps which are turned on and off. This technique results in a true, very low voltage operation without the need for voltage multipliers. As an example, a second order lowpass switched-capacitor filter is implemented in the switched-opamp technique. This filter operates with only a 1.5 V power supply. It is realized in a 2.4-/spl mu/m CMOS process with V/sub T/=/spl plusmn/0.9 V. It has a measured total harmonic distortion of -60 dB for a signal swing of 600 mV/sub ptp/ and a powerdrain of only 110 /spl mu/W. >

High power switched capacitor voltage conversion and regulation apparatus

Abstract: A DC-to-DC voltage convertor is made up of a capacitor array having plural capacitor elements (C p1 , C p2 , C p3 ) and a plurality of switches (S2 . . . S10) which are switchable between at least two states. When the switches are switched in the first state, the capacitor elements are connected in series, and when the switches are connected in the second state, the capacitor elements are connected in parallel. The DC-to-DC voltage convertor may be configured as a step-down convertor (FIG. 2a) or a step-up convertor (FIG. 2b).

Steady-state analysis and design of a switched-capacitor DC-DC converter

Abstract: A representative switched-capacitor DC-DC converter topology is presented, circuit operation is explained, and control strategies are identified. State-space averaging is used to analyze steady-state performance and to develop control criteria and design equations. The analytical results are verified by SPICE simulation. >

Dynamically configurable switched capacitor power supply and method

Abstract: A dynamically configurable switched capacitor power supply and a method for operation thereof. The power supply includes a first dynamically adjustable switched capacitor network having a first input, a first output and including a first plurality of n many switched capacitors. The first input is adapted to be coupled to a power source. The first dynamically adjustable switched capacitor network provides a step-up or step-down power supply regulation function in response to first control signals. The power supply includes a control network having an error detector coupled to the first output, an oscillator for providing a clocking signal, an analog to digital conversion circuit for providing a digital representation of a voltage of the power source and control logic for providing the first control signals in response to the clocking signal and in response to signals from the error detector.

Dynamic response of a thyristor controlled switched capacitor

Abstract: This paper computes the small signal dynamic response of a thyristor controlled series capacitor system for use in flexible AC transmission system control design. The computation includes the effects of synchronization and the nonlinearity due to thyristor switching. Eigenvalues of the small signal dynamic response are computed and used to study the dynamic response of the Kayenta system using different methods of synchronization and a closed loop control. >

Surface micromachined pressure sensors with integrated CMOS read-out electronics

Abstract: In this paper a single chip pressure and tenperature sensor system with on chip electronics is presented. The capacitive pressure sensor is fabricated using a CMOS process with additional surface micromachining steps to form a membranes. The membrane dimensions have been optimized for a pressure range of 2, 3.5, 10 and 35 bars, respectively. The temperature sensor shows a straight linear output signal in a temperature range of 0 to 70 °C. For the signal processing switched capacitor circuits are used. The sensor signals are converted to a pulse width modulated output signal. The silicon chip has an active area of 3.5 mm 2 . Between 0 and 80 °C a temperature dependence of the pressure segnal of less than 200 ppm/°C referring to full scale was found.

Double sampled biquad switched capacitor filter

Abstract: A biquad switched capacitor filter is preferably utilized as the output filter in a sigma delta digital-to-analog converter. The switched capacitor filter uses a cross-coupled switched capacitor circuit which delivers charge to the capacitors on both phases of the clock. As a result, the sizes of the capacitors can be reduced by a factor of two, while delivering the same charge as a single sampling circuit. By using the cross-coupled switching circuit everywhere in the filter, the sensitivity to capacitor mismatches is substantially reduced. The clock phases applied to the stages of the filter are alternated so that there is a one clock cycle delay around each loop containing two filter stages, thereby insuring the stability of the filter.

Demodulation of an IF-signal by a sigma-delta converter

Abstract: A sigma-delta signal converter is implemented using switched capacitor switching elements in which a first switch (31) serves as a mixer (11). The output of the mixer is directed to the second input of an adder (16), and its second input is the feedback signal (f1) of the sigma-delta signal converter, which is also directed into a base-frequency output signal through a decimator (14) and low-pass filtering (15).

Modeling opamp-induced harmonic distortion for switched-capacitor /spl Sigma//spl Delta/ modulator design

Abstract: This communication reports a new modeling of opamp-induced harmonic distortion in SC /spl Sigma//spl Delta/ modulators, which is aimed at the optimum design of this kind of circuit for high-performance applications. We analyze incomplete transfer of charge in a SC integrator and use power expansion and nonlinear fitting to obtain analytical models to represent harmonic distortion as function of the opamp finite gain-bandwidth (GB), slew-rate (SR) and nonlinear DC gain. Calculated models apply for all modulator architectures where harmonic distortion is dominated by the first integrator in the chain. We show that results provided by the new analytical models fit well to that obtained by simulation in time domain and have accuracy levels much larger than that provided by previously reported modeling approaches. >

Analog VLSI implementations of auditory wavelet transforms using switched-capacitor circuits

Abstract: A general scheme for the VLSI implementations of auditory wavelet transforms is proposed using switched-capacitor (SC) circuits. SC circuits are well suited for this application since the dilation constant across different scales of the transform can be precisely implemented and controlled by both the capacitor ratios and the clock frequency. The hardware implementations are made possible by several new circuit designs. Specifically, extremely area-efficient designs are presented to implement very large time-constant filters used to process speech and other acoustic signals. The designs employ a charge differencing technique to reduce significantly the capacitance spread ratios needed in the filter banks. Also, a parasitic-insensitive sum-gain amplifier is designed which samples several inputs at the same phase. The proposed circuits have been fabricated using a 2 /spl mu/m CMOS n-well process with double polysilicon and double metal. In addition, a 32-channel prototype filter bank (each channel is a 6th order transfer function), covering a frequency range from 0.2 to 6.4 kHz which includes 36 biquads, 32 sum-gain amplifiers and a preemphasis highpass filter, is implemented on a 4.6/spl times/6.8 mm/sup 2/ die. The IC measurement results of the proposed circuits and the filter bank show the advantages of such new designs. >

A Long Pulse Modulator For Reduced Size And Cost

Abstract: A novel modulator has been designed, built and tested for the TESLA test facility. This e{sup +} e{sup {minus}} accelerator concept uses superconducting RF cavities and requires 2ms of RF power at 10 pps. As the final accelerator will require several hundred modulators, a cost effective, space saving and high efficiency design is desired. This modulator used a modest size switched capacitor bank that droops approximately 20% during the pulse. This large droop is compensated for by the use of a resonant LC circuit. The capacitor bank is connected to the high side of a pulse transformer primary using a series GTO switch. The resonant circuit is connected to the low side of the pulse transformer primary. The output pulse is flat to within 1% for 1.9 ms during a 2.3 ms base pulse width. Measured efficiency, from breaker to klystron and including energy lost in the rise time, is approximately 85%.

A design-for-test technique for switched-capacitor filters

Abstract: The paper describes a design-for-test technique for switched-capacitor (SC) filters to improve controllability and observability of internal nodes. Timing strategies employing existing clock phases in SC circuits are used to sensitize signal propagating paths, thus enhancing the circuit testability. The overhead in terms of extra control logic is small (several simple gates). Since there are no extraneous devices inserted in the analog signal path, there is no performance penalty in the normal operation of the filters. >

A 700-MHz switched-capacitor analog waveform sampling circuit

Abstract: Analog switched-capacitor memory circuits are suitable for use in a wide range of applications where analog waveforms must be captured or delayed, such as the recording of pulse echo events and pulse shapes. Analog sampling systems based on switched-capacitor techniques offer performance superior to that of flash A/D converters and charge-coupled devices with respect to cost, density, dynamic range, sampling speed, and power consumption. This paper proposes an architecture with which sampling frequencies of several hundred megahertz can be achieved using conventional CMOS technology. Issues concerning the design and implementation of an analog memory circuit based on the proposed architecture are presented. An experimental two-channel memory with 32 sampling cells in each channel has been integrated in a 2-/spl mu/m CMOS technology with poly-to-poly capacitors. The measured nonlinearity of this prototype is 0.03% for a 2.5 V input range, and the memory cell gain matching is 0.01% rms. The dynamic range of the memory exceeds 12 b for a sampling frequency of 700 MHz. The power dissipation for one channel operated from a single +5 V supply is 2 mW. >

Zero-voltage switching in switched current circuits

Abstract: Traditionally the accuracy of switched-current circuits has been much lower than that of switched-capacitor circuits. To address this problem, an accurate high-speed switched-current sample-and-hold technique based on zero-voltage switching is presented. The technique significantly reduces the signal dependent charge injection, leading to improved sampling accuracy. To demonstrate the proposed technique, a sample-and-hold has been implemented using a 1.2 /spl mu/m CMOS process. The circuit is expected to achieve 14 bit linearity at sampling rates exceeding 50 M Samples/sec. While dissipating only 3.5 mW from a nominal 3.3 V supply. >

Auto-zero switched-capacitor integrator

Abstract: A switched-capacitor auto-zero integrator includes and integrator circuit and a correction circuit. The integrator circuit may be any circuit including an operational amplifier having an input line and an output line, an input capacitor coupled to be charged by an Input voltage, an integrating capacitor coupled to the output line, and at least one integrating switch operable during an integrating time interval to connect the input capacitor to the integrating capacitor such that the integrating capacitor is charged to compensate for charge of the input capacitor. The correction circuit includes an offset capacitor coupled to the input line and at least one correction switch operable in an auto-zero sub-interval: and a correction sub-interval. The sub-intervals occur only during the integrating interval such that the offset capacitor is charged by an offset voltage and a gain error voltage of the operational amplifier during the auto-zero sub-interval and the offset capacitor is connected to a summing node between the input capacitor and the integrating capacitor during the correction sub-interval.

Switched capacitor charge pump and sawtooth oscillator using same

Abstract: Charge pump including: a capacitor (4) which includes a first capacitor terminal (2) and a second capacitor terminal (8), a discharge switch (20) for discharging the capacitor (4) by the closing and opening of the discharge switch (20) in response to a first or second value respectively, of a clock signal (CS), a first current source (6) for supplying a first current (I1) to the first capacitor terminal (2), a comparator (12) whose first input (10) is connected to the first capacitor terminal (2) and whose second input (14) is connected to a reference voltage source (16) and which comparator generates a comparison signal (Vcomp) of which a first or second value denotes that the voltage (Vc) on the first input (10) is smaller or larger than the voltage on the second input (14), a current switch (24) passing a second current (I2) coming from the second current source (34) to an output terminal (28) once the clock signal (CS) has changed from the first to the second value, and prevents the second current (I2) flowing to the output terminal (28) once the comparison signal (Vcomp) has changed from the first to the second value. A sawtooth oscillator is formed by using the charge pump as a timing circuit with the oscillator providing the clock signal, and the second current from the output terminal being fed back to the first capacitor terminal.

Unity-power-factor PWM rectifier with DC ripple compensation

Abstract: This paper presents a new topology of PWM rectifier which can achieve unity-power-factor on the AC supply side and ripple-reduction on the DC output side. The main circuit of this rectifier is accomplished by adding only a pair of switches to a conventional PWM rectifier. And it does not need the large DC capacitor or passive L-C resonant circuit. These additional switches and PWM rectifier are controlled not only to make a unity power factor but also to reduce the ripple current. The effectiveness of this circuit is confirmed by the experiments and analysis. This rectifier is useful for UPS and DC power supply, especially in case that the batteries are connected to the DC line. >

Matrix addressed LCD display having LCD age indication, and autocalibrated amplification driver, and a cascaded column driver with capacitor-DAC operating on split groups of data bits

Abstract: A column driver for a matrix addressed display such as a liquid crystal display (LCD) is disclosed. The column driver accepts 10-bit inputs, provides 1024 distinct output levels, and is compatible with digital gamma correction by way of, for example, an EPROM lookup table. A complete column driver includes a group of chips which are serially interconnected and receive all the external signals applied in parallel. Only one chip is made active at any instant of time, in order to save power. In each IC, selective polarity inversion of the 10-bit data is carried out before feeding it to a switched capacitor digital to analog converter (CAPDAC) which operates in either a high or low voltage range. All CAPDACs are loaded simultaneously and present a precise output for approximately 95% of each linetime. Each CAPDAC output is connected to a buffer opamp via two CMOS switches which cause the CAPDAC to simultaneously yet transparently change range and allow the opamp buffer to continue driving. The buffer accepts a high impedance, low parasitic input voltage from the CAPDAC array and outputs a low input signal for driving columns with 150-400 pF capacitance. The buffer has an autocalibration circuit that comprises a nested, mini-operational amplifier (opamp) coupled between the output and input of the buffer. The mini-opamp amplifies the balance error produced by the buffer during a calibration interval to provide an output signal which changes the balance point of the buffer amplifier.

Accurate SI filters using RGC integrators

Abstract: The design and implementation of single-ended and fully-differential switched current (SI) biquadratic high-Q bandpass filters to meet the specifications of the dual-tone multiple-frequency (DTMF) system are presented. Both designs use the regulated-gate cascode (RGC) dynamic current mirror to obtain center frequency accuracy of 0.1% and a quality factor of 24. Compared to the equivalent switched capacitor (SC) implementation of these filters, the single-ended SI filter requires 30% less area for the same minimum-sized capacitance, power dissipation and performance. >

An 8 MHz, 80 Ms/s switched-current filter

Abstract: Since its introduction in 1989, the switched-current (SI) technique for sampled-data signal processing has claimed the advantage over switched-capacitors of needing only digital CMOS processing, making it cheaper and more amenable to mixed-signal ICs. Attempts to raise the performance to match that of switched-capacitors has had mixed success, and some silicon implementations have been reported. A recent advance, called S/sup 2/I, promises the highest overall performance yet. This paper demonstrates that switched current filters can not only compete with switched-capacitors and use simpler IC processing but also perform well with sampling frequencies of at least 80 MHz. >

Low voltage, switched capacitance circuit employing switched operational amplifiers with maximized voltage swing

Abstract: A switched capacitance circuit, using a switched operational amplifier structure as an input switch of the switched capacitance, is provided with a new biasing circuit. An additional switched capacitor, switched alternately to power supply and to ground, is connected to the output side of the primary switched capacitor. Precision is retained while ensuring a rail-to-rail dynamic range, without requiring boosted control phases. Special arrangements may be implemented for controlling the amplitude of switching spikes when so required. A fully differential embodiment is also feasible with additional advantages.

Programmable switched capacitor circuit

Abstract: A switched capacitor circuit is described which is programmable so that its function can be set by a user. Thus, control circuitry and selection circuitry are provided to enable one of a plurality of alternative control signals to be provided to switch circuits of the switched capacitor circuit. In this way, the function of the switched capacitor circuits can be altered. Where there are a plurality of switched capacitor circuits connected in an array, the topology of the array can be altered by suitably routing particular input signals to particular outputs by selecting the control signals to control the switched circuits. A field programmable array of this type is also described.

A 126 dB linear switched-capacitor delta-sigma modulator

Abstract: Low-frequency measurement applications where low power, high dynamic range and high linearity are important naturally migrate toward oversampling converters. Measuring seismic activity is one such application that requires at least 120 dB S/D. The switched-capacitor delta-sigma modulator presented in this paper achieves the above goals with single-ended linearity in excess of 120 dB. Various distortion mechanisms in switched-capacitor topologies are explained along with solutions. >

Dynamically balanced fully differential circuit for use with a battery monitoring circuit

Abstract: A battery detect circuit (32) is provided that is operable to dispose a sense resistor (50) in series with the battery to determine whether the charge is being provided to the battery or being extracted from the battery. The voltage across the sensor resistor (50) is sensed by a voltage/frequency converter (52). The voltage/frequency converter (52) is a differential structure comprised of two integrator structures (102) and (104) that are operable to utilize a switched capacitor configuration to drive comparators on the output thereof. Each of the integrator structures (102) and (104) has associated therewith passive elements and active elements. The integrators (102) and (104) have associated therewith integration capacitors (147) and (149). Additionally, there are two operational amplifiers (143) and (145) that provide the active components of each of the integrators (102) and (104). The various switched capacitor circuits (161) and (163) associated with the amplifiers (143) and (145) are provided to provide the integration operation. Both the amplifiers (143) and (145) and their associated switched capacitor circuits (161) and (163) are dynamically balanced such that they are switched between integrator (102) and integrator (104) on a periodic basis. This therefore allows the errors between the active and passive elements to be switched between the two integrators (102) and (104) such that no accumulative error occurs.

Sigma-delta modulator having reduced delay from input to output

Abstract: Described herein is a fourth-order sigma-delta modulator which utilizes two second-order sigma-delta modulators connected together. Each second-order sigma-delta modulator is characterized as including integrators having a 1/2 sample period delay from input to output. A second-order sigma-delta modulator, including such integrators, exhibits a single sample period delay from input to output. A fourth-order sigma-delta modulator, which includes two such second-order sigma-delta modulators, exhibits a delay of two sample periods from input to output. The present sigma-delta modulator can be fabricated using switched capacitor circuitry to form an A/D convertor, and in another embodiment can be used as a digital noise shaper for a D/C convertor circuit. The 1/2 unit delay is implemented without requiring two D-flip flops in series, which results in a design and manufacturing advantage.

Analog circuit synthesis for large, realistic cells: designing a pipelined A/D converter with ASTRX/OBLX

Abstract: ASTRX/OBLX are a pair of synthesis tools that together can size high-performance analog circuit topologies to meet user supplied performance constraints. Previous approaches to cell synthesis have focused almost exclusively on small linear textbook circuits, e.g. classical op amps with 5-10 devices. In contrast, in this paper we describe our successful experiences with fully automatic synthesis of the largest analog cells automatically created to date. We design a comparator and a switched capacitor gain cell (82 devices in total), and use them to complete a realistic pipelined A/D converter. >

A switched capacitor circuit simulator: AWEswit

Abstract: This paper describes the modeling and simulation of switched capacitor circuits in AWEswit. AWEswit is a mixed signal simulator for switched capacitor circuits. It allows for portions of the circuit to be modeled with digital blocks controlled by an event queue. The remainder of the circuit is modeled in the analog domain. The paper describes the circuit formulations employed by AWEswit, and how they are exploited in modeling the nonidealities associated with switched capacitor circuits. AWEswit employs asymptotic waveform evaluation (AWE) as its core simulation engine. It combines circuit formulations in the charge-voltage and current-voltage regimes. This flexibility in the circuit formulations means that if the circuit is modeled entirely with ideal switches (i.e. no resistors), then it is automatically solved in the charge-voltage regime (like SWITCAP2). However, if portions of the circuit need to be solved in the current-voltage regime, then AWEswit automatically partitions the circuit and solves the different partitions in whichever regime is appropriate, i.e., in the current-voltage regime (using AWE to evaluate circuit response) or in the charge-voltage regime. AWEswit naturally handles the bandwidth limitations associated with switched capacitor circuits. In addition, it models the clock feedthrough and signal-dependent charge dump that characterize MOSFET switches. The simulator is illustrated by example. >

Operation and design of a switched-capacitor DC-DC converter with improved power rating

Abstract: This paper shows that a switched-capacitor DC-DC converter can be designed to process up to several tens of watts of output power at an efficiency exceeding 80%. Converter operation is analyzed by "modified state-space-averaging", which is generally suitable for analysis of converters with nonlinear ripple. A design procedure is presented along with experimental verification. >

A high-slew integrator for switched-capacitor circuits

Abstract: A new method for improving the slew rate of a switched-capacitor integrator is introduced. A booster circuit is used to measure the integrator input voltage and then inject a proportionate amount of charge at the integrator output. The boosted integrator significantly reduces the settling time due to amplifier slewing. In addition, the booster has no adverse effect on the noise and stability performance of the integrator. The booster stage increases the total static integrator power by 36% and the total die area by 22%. >

Multistage bandpass delta sigma modulators

Abstract: A new architecture for oversampled delta sigma A/D conversion of high-frequency narrow band signals using cascaded low-order stages to obtain high overall order of noise shaping is described. The architecture involves using resonators in individual stages to suppress quantization noise at the resonant frequency. Many of the problems of previous single stage high-order architectures including poor stability, large component spread and design complexity are overcome by this new approach. Switched capacitor resonator circuit implementations and simulation results for a sixth-order modulator example are included. Estimates of the potential for 16-bit A/D conversion of 2.5 MHz signals exceed the 80 KHz capability of existing monolithic oversampled CMOS A/Ds. >