Showing papers on "Switched capacitor published in 1996"

Sensor circuit for providing maximum and minimum cell voltages of a battery

Abstract: A sensor circuit is provided for monitoring four cells of a battery. The sensor circuit provides a maximum terminal cell voltage and a minimum terminal cell voltage. In a switched capacitor embodiment, one comparator compares the cells, two at a time. The output of the comparator is provided to a maximum state machine and a minimum state machine which select the cells with the highest and lowest voltages, respectively. In a continuous system embodiment, six comparators continuously monitor the cell voltages. The comparator outputs are provided to a maximum logic circuit and a minimum logic circuit which select the cells with the highest and lowest voltages, respectively, and provides a maximum and a minimum terminal voltages signals. These maximum and minimum terminal voltage signals are provided so that a charge controller can monitor the cells for overcharge and discharge conditions.

Switched-capacitor power supplies: DC voltage ratio, efficiency, ripple, regulation

Abstract: A comprehensive and accurate steady-state analysis of a step-up DC-DC switched-capacitor power converter is performed. No approximations, such as average techniques, are invoked. Parasitic elements such as diode forward voltages, on-resistances of transistors and equivalent-series resistances of capacitors are included into the model. The converter performance functions, i.e. DC voltage ratio, efficiency, output voltage ripple, are expressed in terms of the number of switched-capacitor stages, number of capacitors per stage, values of the capacitors and parasitic elements, switching frequency and load. Design criteria aiming at high efficiency, low ripple and achievable output voltage are formulated. Trade-offs between the efficiency requirement and good regulation capability are discussed.

Switched-capacitor DC/DC converters with resonant gate drive

Abstract: In this paper, we examine how switched-capacitor (SC) converters can be used in low-voltage low-power DC/DC applications with power management. Analysis of losses is presented to facilitate SC converter design and optimization. A resonant gate drive is proposed to reduce switching losses and simplify control of switches in SC converters. A closed-loop controller is designed to enable and disable oscillations of the resonant gate drive so that the output DC voltage is well regulated down to zero load and so that high efficiency is maintained for a very wide range of loads. Results are experimentally verified on two low-power (0.2 and 5 W) five-one step-down converters with regulated 3 Vdc output and efficiency greater than 80% in a 100-1 load range.

Biquadratic switched-capacitor filter using single operational amplifier

Abstract: The present invention discloses a biquadratic switched-capacitor filter, which merely utilizes one operational amplifier to implement a biquadratic transfer function. The biquadratic switched-capacitor filter further comprises ten switched-capacitor circuits, two feedback capacitors, and two individual switching devices. The switching devices in this switched-capacitor filter can be controlled by six different clock signals. The first and second clock signals are two-phase, complementary but non-overlapping pulse trains with a reference period. The third clock signal is a pulse train with double the reference period and coincident with the first clock signal. The fourth, the fifth, and the sixth clock signals are pulse trains that result from delaying the third, the fourth, and the fifth clock signals by half the reference period. The obtained switched-capacitor filter can be used to simplify some applications, such as sigma-delta modulators.

1.2 V CMOS switched-capacitor circuits

Abstract: In battery-powered portable systems, low-voltage CMOS integrated circuits are essential for low power consumption. While integrating analog and digital circuits on the same chip, it is preferred that both analog and digital circuits share the same voltage supplies. However, a low supply voltage forces severe constraints on the design of analog circuits and the conventional CMOS transmission gates may no longer be adequate or even functional as analog switches if the signal swing of the switch control is kept between the nominal supply voltages. Design techniques for 1.2 V CMOS switched-capacitor (SC) circuits are described. MOS transistors with low-threshold voltages are not required. The signal paths are fully differential to maximize noise immunity against disturbances from supplies and substrate, critical when a large number of digital circuits are on the same chip. The analog switches are implemented with nMOS transistors. An on-chip high-voltage generator is used to generate the high-voltage required to turn on the nMOS switches. The circuits use a 0.8 /spl mu/m n-well double-poly double-metal CMOS technology. The threshold voltages are 0.7 V for the nMOSTs, and -0.8V for the pMOSTs.

Baseband filters for IS-95 CDMA receiver applications featuring digital automatic frequency tuning

Abstract: This paper presents fully-integrated dual (I and Q) low-pass seventh-order Chebychev continuous-time filters for IS-95 CDMA channel selection applications. The capabilities of digital signal processors, available in almost all modern transceivers, are exploited to adapt the filter bandwidth to the desired frequency with minimum additional hardware. To fulfill the requirement of handling signals with a wide dynamic range, an active RC filter topology is adopted. Digital tunability is provided by constructing each integrating capacitor with an array of binary-weighted capacitors. The capacitors are switched in or out under the control of the DSP. The ratio of the fixed capacitor to the total variable capacitors is chosen based on the expected RC time-constants variations.

Practical design methodology of auxiliary resonant snubber inverters

Abstract: This paper describes the design methodology for auxiliary resonant snubber inverters including /spl Delta/- and Y-configured auxiliary resonant snubber inverters. The design emphases are resonant circuit components including inductor, capacitor, end switch, DC link capacitor, and control technique. Design optimization can be aimed at high efficiency, high frequency, low dV/dt, or compact size. An example of designing a three-phase 100 kVA unit is described step by step. Hardware implementation and experimental results are shown for verification.

Sampled data simulation of linear and nonlinear circuits

Abstract: In this paper, an efficient, accurate, stable, and explicit method for transient analysis of lumped linear time invariant circuits is given. The method formulates a set of finite difference equations in the analog domain for sampled data simulation of the circuit. The solution of these equations gives the network response at fixed and equally spaced discrete instants of time. The fixed-time interval between each solution can be chosen arbitrarily and does not depend on the circuit time constants. The transient solution at each time point requires one matrix/vector multiplication and vector addition only. The algorithm is a general computer oriented formulation method that can be applied to any linear circuit. In addition to linear time invariant circuits, the method can be applied to a restricted class of time varying and/or nonlinear circuits. It is directly applicable to linear networks containing periodically clocked ideal switches, for example, switched capacitor and switched current circuits. In these networks, the circuit is linear inside each phase and changes its topology at fixed discrete instants of time. All nonlinear elements allowed in analysis must be clocked, such that their characteristics change only at discrete instants of time. For example, clocked digital circuits, such as, ideal comparators, A/D and D/A blocks are allowed. In particular, the method is applied to the simulation of oversampled delta-sigma modulators. The method can be used to study the effect of clock feed through, finite switch resistance, and finite gain bandwidth of operational amplifiers on the performance of these modulators. In addition, the algorithm can be used for analysis of continuous time delta-sigma modulators. Examples of simulation results are given.

A field-programmable analog array (FPAA) using switched-capacitor techniques

Abstract: We present a voltage-mode switched-capacitor approach to the design of Field Programmable Analog Arrays (FPAA). The designed FPAA consists of uniform configurable analog blocks (CABs) which allow the implementation of different functions. The CABs are connected to each other via switched and unswitched capacitors. The internal structure of CABs and the interconnection network between them are configured by user-programmable digital control signals. The functionality of the FPAA is verified by embedding of different filters, programmable amplifiers, biquads, modulators and signal generators.

Switched capacitor gain stage

Abstract: A switched capacitor gain stage (21) that samples an input voltage every clock cycle phase for effectively doubling the frequency of operation. The switched capacitor gain stage (21) comprising an amplifier (22), a first capacitor network, and a second capacitor network. Either the first or second capacitor network is sampling an input voltage. For example, the first capacitor network samples an input voltage. Capacitors of the first capacitor network are coupled to sample the input voltage via switches. Capacitors of the second switched capacitor network are coupled around the amplifier (22) in a gain configuration via switches. The capacitors of the second switched capacitor network having a voltage stored from a previous clock phase. In a next clock phase the second switched capacitor network are coupled via switches for sampling an input voltage and the first switched capacitor network is coupled via switches in a gain configuration around the amplifier (22).

Switching-mode DC-DC converter with switched-capacitor-based resonant circuit

Abstract: A soft-switching dc-dc converter, in which the resonant capacitor is replaced by a switched-capacitor circuit, is presented. The new system incorporates a switching technique at zero-current or zero-voltage for each switch and an operation at constant switching frequency. The first feature is due to the presence of a resonant circuit, which shapes the switches' current and voltage waveforms in a sinusoidal form. It assures minimal switching losses. The switched-capacitor circuit determines a simple, discrete control, extends the region in which the soft-switching condition is fulfilled to large values of the load or small values of the input voltage, and prevents the current stress on the electronic devices from increasing with the input voltage. An original design approach allows for choosing the element values so as to get both soft-switching and regulation over a large range of input voltage and load values. Analysis, computer simulation and experiments indicate the operation principles of the new structure and render evident its performances, such as high efficiency and good regulation capability.

Switched capacitor input sampling circuit and method for delta sigma modulator

Abstract: A switched capacitor input sampling circuit in a chopper stabilized delta sigma modulator includes first and second input terminals adapted to receive a differential analog input voltage therebetween and first and second terminals coupled to first and second charge summing conductors, respectively, of the delta sigma modulator. The switched capacitor input sampling circuit also includes a first switch coupled between the first input terminal and a first conductor, a second switch coupled between the second input terminal and a second conductor, a third switch coupled between the first conductor and a bias voltage conductor, a fourth switch coupled between the second conductor and the bias voltage conductor, a first input capacitor coupled between the first conductor and a third conductor, a second input capacitor coupled between the second conductor and a fourth conductor, a fifth switch coupled between the third and fourth conductors, a sixth switch coupled between the third conductor and the first charge summing conductor, and a seventh switch coupled between the fourth conductor and the second charge summing conductor.

Standard cell having a capacitor and a power supply capacitor for reducing noise and method of formation

Abstract: An integrated circuit (10), which is designed using standard cells (20, 22, 24, 26, 28, 30, 32, 34, 35, 36, 37, 28, 40, 42, 44, 46, 48, 50, 52), usually has one or more empty spaces (54) wherein no circuitry is formed. These empty spaces may be used to form capacitor standard cells which have capacitors (see FIGS. 3 and 4) to both ground and power supply lines within the integrated circuit. These capacitors are used to reduce noise in the power and supply lines in a manner more useful/efficient than known methods. The capacitor standard cell taught herein is more useful/efficient due to the fact that the capacitance provided by these standard cells is distributed over the entire integrated circuit in small portions (i.e., standard cells are placed all over the integrated circuit (10)), and is placed close to the logic which is switching. It is the switching logic which is the root of a large portion of internal integrated circuit noise.

Design and Implementation of a Field Programmable Analogue Array

Abstract: A Field Programmable Analogue Array (FPAA) is presented based on switched capacitor technology. The chip allows true array programming of undedicated analogue cells. There is provision for internal signal-conditional switching as part of the normal function of the array. With the presented chip it is possible to implement a very wide range of analogue signal processing functions such as data conversion, linear signal processing and non-linear functions. These functional configurations can be reconfigured and parameterised on the fly during concurrent signal processing. Very rapid prototyping of switched capacitor circuits is facilitated. The field programmable nature of the chip allows several markets/customers to be targeted simultaneously with obvious benefits in terms of both volume of sales and reduced time to market.

Driving circuit for light emitting element

Abstract: In a circuit for driving a light emitting element, a switched capacitor circuit including a capacitor is connected between a power supply and the light emitting element. The capacitor in the switched capacitor circuit is charged to a power supply voltage when switches are exchanged to the sides of charging. The power supply is connected in series with the capacitor when the switches in the switched capacitor circuit are exchanged to the side of discharging. The power supply and capacitor connected in series therewith supplies the driving current to the light emitting element. Changing the number of times of exchange of the switches permits the driving current to flow into the light emitting element to be varied. Thus, the circuit for driving a light emitting element with excellent power-supply efficiency is provided which can drive a light-emitting element even when the power supply voltage for driving the light emitting element is lower than the forward voltage thereof.

Analog signal sampler for imaging systems

Abstract: An analog signal sampler with improved correlated double sampling (CDS) performance for imaging systems includes a dual mode input amplifier, a switched capacitor network and a differential amplifier. The dual mode input amplifier has a high input impedance and allows for receiving either positive-going contact image sensor (CIS) or negative-going charge couple device (CCD) image signals as desired. The switched capacitor network and differential amplifier together perform an improved CDS of the image signal and convert the unipolar input image signal to a bipolar differential output signal with an improved dynamic signal range. The CDS technique used relies upon simultaneous charging of the coupling and sample and hold capacitances with charge transfer from the coupling capacitance to the sample and hold capacitance. The gain of the sampler can be programmed by appropriate selection of the ratio of the coupling capacitance to the sample and hold capacitance.

High speed fully differential operational amplifier with fast settling time for switched capacitor applications

Abstract: A high speed fully differential operational amplifier with fast settling time for switched capacitor applications includes a high gain active cascode applied to the operational amplifier's input stage transistors to improve the gain, provide a higher output impedance, and thus, reduce the Miller feedback gate drain capacitance of the input stage devices. This improves the speed of the amplifier. A biasing technique is used to keep the active cascodes biased during transient overload so that settling will not be adversely affected during the recovery of the cascodes. A pair of transistors are used to feed forward a fraction of the tail current to "keep-alive" the cascode transistors. In other words, the fraction of the tail current that is fed to the source of the cascode transistors via the keep-alive transistors effectively biases the active cascodes sufficiently so that they do not turn off completely during slewing.

Implementing transmission zeroes in narrowband sigma-delta A/D converters

Abstract: In accordance with the present invention, circuits are disclosed for use in implementing higher order sigma delta analog to digital conversion of narrowband signals with cascaded lower order circuit networks. The lower order circuit networks employ resonator circuits utilizing unit delay functional blocks to implement a specific transfer function. The unit delays are implemented utilizing sample and hold circuits operated by controlled switching of the circuit elements. In one embodiment, the resonator circuit includes a first sample and hold circuit for implementing a unit delay of corresponding input signals where the output of the first sample and hold circuit is coupled into a feedback loop with one or more additional sample and hold circuits for implementing a dual cascaded unit delay. The delayed signals from the feedback loop are then summed with the input signals at the input of the first sample and hold circuit. Advantageously, the present invention overcomes performance limitations of complex higher order sigma delta analog to digital converters that suffer from circuit nonidealities such as component mismatch, finite operational amplifier gain, bandwidth and design complexities associated with integrator based implementations. Alternate embodiments of the present invention include a switched capacitor based circuit for implementing the lower order delay function block based networks and a current copier or switched current approach. The switched capacitor circuit employs a first operational amplifier for inputting signals and summing with delayed samples of the input signals and a second operational amplifier coupled in a feedback loop with the first operational amplifier for implementing the delayed samples of the input signals. The switched current circuit employs a first current copier for sampling input signals and summing with a delay of the input signals. Second and third current copiers are used for implementing delayed sampling and holding for two separate signals output from the first current copier. The sampling, holding, delaying and summing are implemented with controlled switching in the circuits.

A -80 dB THD, 4 V/sub pp/ switched capacitor filter for 1.5 V battery-operated systems

Abstract: A fully differential fifth-order SC filter that can operate from power supplies as low as 1.5 V featuring a -80 dB THD up to 4 V/sub pp/ output voltage is presented. A measured p-weighted noise of 120 /spl mu/V/sub rms/ leads to a dynamic range of 81.5 dB. This circuit is used as reconstruction filter for a low voltage 14-b DAC. The very low voltage operation has been possible by integrating a regulated voltage-multiplier on the same chip. The filter active area is 0.54 mm/sup 2/ in a 0.8 /spl mu/m CMOS technology. Typical power consumption is 0.8 mW at 1.5 V supply.

Switched capacitor filter

Abstract: A switched capacitor filter for applying a filter processing including an integration processing to input analog signals of plural channels on a time shared basis includes an integration sections for sequentially implementing the integration processing for the respective channels on a time shared basis, integrated value storage sections for storing integrated value signals representing results of the integration processing for the respective channels, switches for causing, each time the integration processing for the respective channels is interrupted, an integrated value signal representing result of the integration processing for the particular channel at the time of interruption to be stored in the integrated value storage sections and initializing the result of the integration processing by the integration section and, each time the integration processing for the respective channels is implemented, supplying the integrated value signal for the particular channel from the integrated value storage sections to the integration section and supplying also an analog signal to be processed in the integration processing to the integration section.

Multirate and Multiphase Switched-capacitor Circuits

Abstract: Preface. Introduction. Basic element of SC circuits. Discrete-time systems. Multirate systems. Systems with nonuniformly sampled signals. Analysis of multiphase switched-capacitor networks. FIR switched-capacitor. IIR switched-capacitor filters. Applications of multirate and multiphase SC circuits. References.

Microcontroller chip with integrated LCD control module and switched capacitor driver circuit

Abstract: Apparatus for providing multiple of discrete voltage levels to drive a liquid crystal display (LCD) from an LCD module on board a microcontroller chip includes a charge pump with a switched-capacitor that develops the discrete voltages as multiples of the value of a base voltage that remains substantially without change irrespective of change in the supply voltage. A switched-capacitor charging circuit selectively charges a capacitor to produce successive additive charges individually retrievable from the capacitor. An LCD drive selectively transmits the discrete voltage levels to activate the LCD according to status of an external system under the control of the microcontroller. Voltage losses that may occur during the switched-capacitor charging are compensated to maintain the levels of the discrete voltages free of decay. Compensation is achieved by overcharging the capacitor by an amount substantially equivalent to the amount of voltage loss on the capacitor, using active feedback obtained from monitoring the charge on the capacitor.

Differential switched capacitor filtering

Abstract: A differential switched capacitor filter section which comprises a differential amplifier (OTA), a first set of switched capacitors (C11, C12) coupled between a non-inverting output (+) and an inverting input (-) of the differential amplifier (OTA), and a second set of switched capacitors (C21, C22) coupled between an inverting output (-) and a non-inverting input (+) of the differential amplifier (OTA). In the sets of switched capacitors (C11, C12; C21, C22), first terminals of the capacitors are coupled to a corresponding one of the outputs (+; -) of the differential amplifier (OTA) thru first switches (S1.11, S1.12; S1.21, S1.22), and to one of the differential inputs (Vin+; Vin-) of the filter section thru second switches (S2.11, S2.12; S2.21, S2.22). Second terminals of the capacitors are coupled to a corresponding one of the inputs (-, +) of the differential amplifier (OTA) thru third switches (S3.11, S3.12; S3.21, S3.22), and to a reference terminal thru fourth switches (S4.11, S4.12; S4.21, S4.22). Within each set, corresponding switches operate at mutually differing switching phases (ζ1; ζ2).

Combination shared capacitor integrator and digital-to-analog converter circuit with data dependency cancellation

Abstract: A modulator, in conjunction with a load circuit, is provided The modulator forms part of an A/D converter system The modulator includes a series of switched capacitors connected in a shared capacitor arrangement The shared capacitors receive samples from an input signal and, depending upon the logic value fed into a D/A converter, the shared capacitor further receives a feedback reference voltage The reference voltage is thereby coupled to the switched capacitor network, as well as to a load circuit which cancels data-dependent values modulated upon the reference voltage supply The load circuit thereby serves to eliminate ac components within the reference voltage supply resulting from data dependent loading

Multi-function block for a switched current field programmable analogue array

Abstract: This paper presents a Field Programmable Analogue Array (FPAA) based on switched-current (SI) signal processing technology. A design methodology for building complex switched current circuits using a four phase clock is proposed. A programmable building block; called the "Multi-function Block", has been designed and can be used in a FPAA to implement circuits based on this four phase technique. The block was fabricated using 0.7 /spl mu/m CMOS and test results are presented Simulation software for circuits built using these MFBs was written in C++. Example circuits, their implementation using MFBs and simulation results generated by this software are also presented.

Digitally programmable switched current filters

Abstract: A new design technique for switched current filters is presented. The basic element of the filter is a current mirror that employs MOS transistors and an operational amplifier. Programmability of the current mirror is obtained through MOSFET-only current dividers. User programmable analog functions in digital CMOS technology is the main envisaged application for the proposed technique.

Demodulation of an intermediate frequency signal by a sigma-delta converter

Abstract: A sigma-delta signal converter is implemented using switched capacitor switching elements in which a first switch (31) serves as a mixer (11). The output of the mixer is directed to the second input of an adder (16), and its second input is the feedback signal (f1) of the sigma-delta signal converter, which is also directed into a base-frequency output signal through a decimator (14) and low-pass filtering (15).

A 3.3 V 625 kHz switched-current multiplier

Abstract: This paper presents a switched-current multiplier, designed for 3.3 V supply voltage, performing 0.625 M multiplications per second with a maximum nonlinearity of 0.94%. The die area is 100/spl times/75 /spl mu/m/sup 2/ in a 2.4 /spl mu/m n-well CMOS process.

Analog electronic cochlea design using multiplexing switched-capacitor circuits

Abstract: A new design methodology is proposed to realize a real cochlea using the multiplexing switched-capacitor circuits. The proposed technique is based upon the transmission-line model proposed by Zwislocki (1950). At the cost of the increase in the number of clock phases, the decay rate in the transition region of the filter section can be increased by adding only a few components. Therefore, the components and chip area of the designed silicon cochlea can be small. An experimental chip containing four filter sections has been designed and fabricated. The measured frequency responses from the 32-section cochlea formed by cascading nine fabricated chips are consistent with both theoretical calculation results and observed behavior of a real cochlea. Moreover, the designed silicon cochlea has the dynamic range of 67 dB in each section and a low sensitivity to process variations. Thus it is suitable for VLSI implementation with the associated neural network.

Digital to analog conversion system

Abstract: A digital to analog conversion system (10) includes a noise shaper (14) and a digital to analog converter (16). The digital to analog converter (16) includes a series of weighted taps (32, 102) with switched capacitor circuitries (42, 106, 108). The digital to analog converter (16) also includes an amplifier (36, 120) having an associated integrating capacitor (62, 122, 130). The switched capacitor circuitries (42, 106, 108) include capacitors (46) that are coupled in parallel to integrating capacitors (62, 122, 130) by common busses (34, 114, 115).