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Showing papers on "Switched capacitor published in 1997"


Proceedings ArticleDOI
23 Feb 1997
TL;DR: A clocked switched-capacitor circuit can exchange charge between adjacent batteries in a series string, without regard to component values, battery technology, or state of charge as mentioned in this paper.
Abstract: A clocked switched-capacitor circuit can exchange charge between adjacent batteries in a series string. This exchange drives all batteries to identical voltages, without regard to component values, battery technology, or state of charge. This equalization process can proceed while the batteries are in use or under charge, or separately. Transformer-based and transformerless implementations are given, and results of experimental tests are provided. The process is much faster and less stressful than the conventional approach, and is simpler than some active approaches.

480 citations


Patent
28 Apr 1997
TL;DR: In this paper, a monolithically integrated switched capacitor bank using MEMS technology that is capable of handling GHz signal frequencies in both the RF and millimeter bands while maintaining precise digital selection of capacitor levels over a wide tuning range is presented.
Abstract: A monolithically integrated switched capacitor bank using MEMS technology that is capable of handling GHz signal frequencies in both the RF and millimeter bands while maintaining precise digital selection of capacitor levels over a wide tuning range. Each MEMS switch includes a cantilever arm that is affixed to the substrate and extends over a ground line and a gapped signal line. An electrical contact is formed on the bottom of the cantilever arm positioned above and facing the gap in the signal line. A top electrode atop the cantilever arm forms a control capacitor structure above the ground line. A capacitor structure, preferably a MEMS capacitor suspended above the substrate at approximately the same height as the cantilever arm, is anchored to the substrate and connected in series with a MEMS switch. The MEMS switch is actuated by applying a voltage to the top electrode, which produces an electrostatic force that attracts the control capacitor structure toward the ground line, thereby causing the electrical contact to close the gap in the signal line and connect the MEMS capacitor structure between a pair of output terminals. The integrated MEMS switch-capacitor pairs have a large range between their on-state and off-state impedance, and thus exhibit superior isolation and insertion loss characteristics.

185 citations


Journal ArticleDOI
TL;DR: In this article, a new topology for a PWM rectifier which achieves unity power factor on the AC supply side and ripple reduction on the DC output side is presented. But it does not require a large DC capacitor or a passive LC resonant circuit.
Abstract: This paper presents a new topology for a pulsewidth modulation (PWM) rectifier which achieves unity power factor on the AC supply side and ripple reduction on the DC output side. The main circuit of this rectifier consists of a conventional PWM rectifier and a pair of additional switches. The switches and PWM rectifier are controlled such that the ripple current on the DC line is reduced, and unity power factor is achieved on the AC line. As a result, this circuit does not require a large DC capacitor or a passive LC resonant circuit. Furthermore, control of the additional switches and PWM rectifier requires only a simple control circuit. The effectiveness of this circuit was confirmed by experiments and analysis. The rectifier is useful for uninterruptible power systems (UPSs) and DC power supplies, especially for cases in which batteries are connected to the DC line.

175 citations


Patent
20 May 1997
TL;DR: In this article, a switched capacitor system for automatic battery equalization can be used with series coupled batteries (B) as well as primary and backup batteries which are alternately couplable to a load.
Abstract: A switched capacitor system (10) for automatic battery equalization can be used with series coupled batteries (B) as well as primary and backup batteries which are alternately couplable to a load. The system includes a plurality of capacitors (14) and a plurality of switching elements (16). Each of the capacitors is switched back and forth between a predetermined pair of batteries for the purpose of transferring charge therebetween and equalizing the output voltages of each of the batteries in the pair. The capacitors and switching element can be configured in a modular fashion. Multiple modules can be used, for example, in combination with multiple batteries which are series coupled to one another. The system could be used in electric vehicles and in battery backup systems of all types.

145 citations


Journal ArticleDOI
TL;DR: In this article, a formal study of the theoretical performance of switched-capacitor (SC) dc-dc voltage multiplier circuits is given, and a question concerning the necessary number of circuit elements to realize a given conversion ratio is addressed.
Abstract: A formal study of the theoretical performance of switched-capacitor (SC) dc-dc voltage multiplier circuits is given. A question concerning the necessary number of circuit elements to realize a given conversion ratio is addressed. In response to the question the bound on attainable voltage ratio for a given number of capacitors k and the bound on the number of switches required in any circuit configuration have been established. The maximum step-up or step-down ratio is given by the kth Fibonacci number, while the bound on the number of switches required in any SC circuit is 3k-2. The complete set of attainable DC conversion ratios is found. A canonical circuit realization of the maximum voltage ratio is discussed and illustrative examples are included. Necessary and sufficient conditions for the realizability of a dc conversion ratio are determined and formal proofs are given.

145 citations


Journal Article
TL;DR: In this paper, a formal study of the theoretical performance of switched-capacitor (SC) dc-dc voltage multiplier circuits is given, and a question concerning the necessary number of circuit elements to realize a given conversion ratio is addressed.
Abstract: A formal study of the theoretical performance of switched-capacitor (SC) dc-dc voltage multiplier circuits is given. A question concerning the necessary number of circuit elements to realize a given conversion ratio is addressed. In response to the question the bound on attainable voltage ratio for a given number of capacitors k and the bound on the number of switches required in any circuit configuration have been established. The maximum step-up or step-down ratio is given by the kth Fibonacci number, while the bound on the number of switches required in any SC circuit is 3k-2. The complete set of attainable DC conversion ratios is found. A canonical circuit realization of the maximum voltage ratio is discussed and illustrative examples are included. Necessary and sufficient conditions for the realizability of a dc conversion ratio are determined and formal proofs are given.

138 citations


Patent
22 Dec 1997
TL;DR: In this paper, a desired frequency response of a microwave network on a monolithic microwave integrated circuit (MMIC), a MIC, or a hybrid circuit is achieved by selectively switching MEM switches to change the network topology.
Abstract: A desired frequency response of a microwave network on a monolithic microwave integrated circuit (MMIC), a microwave integrated circuit (MIC), or a hybrid circuit is achieved by selectively switching MEM switches to change the network topology. In a filter network, MEM switches connected between capacitors and inductors are selectively switched to change the network configuration to achieve a desired frequency response. In an amplifier network, the MEM switches are selectively switched to tune the amplifier to a desired frequency response and to reduce harmonic output.

88 citations


Journal ArticleDOI
TL;DR: This paper reports a 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit using two bootstrap capacitors to enhance the switching speed for low-voltage CMOS VLSI.
Abstract: This paper reports a 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit using two bootstrap capacitors to enhance the switching speed for low-voltage CMOS VLSI. For a supply voltage of 1.5 V, the full-swing bootstrapped CMOS driver circuit shows a 2.2 times improvement in switching speed in driving a capacitive load of 10 pF as compared to the conventional CMOS driver circuit. Even for a supply voltage of 1 V, this full-swing bootstrapped CMOS large capacitive-load driver circuit is still advantageous.

75 citations


Journal ArticleDOI
TL;DR: In this paper, a circuit family including a dependent switched capacitor (DSC) is discussed, and the DSC function is instantaneously short of one capacitor at the moment when its voltage reaches a threshold.
Abstract: This paper discusses a circuit family including a dependent switched capacitor (DSC). The DSC function is instantaneously short of one capacitor at the moment when its voltage reaches a threshold. The chaos generation can be guaranteed theoretically. We also consider a master-slave system. If there does not exist a homoclinic orbit in the master chaos attractor, it exhibits either in-phase or inverse-phase synchronization of chaos. If there exists a homoclinic orbit, the synchronization is broken down. We explain the synchronization mechanism and evaluate its robustness theoretically. The theoretical results have been verified in laboratory experiments.

71 citations


Patent
12 Sep 1997
TL;DR: In this article, a bandpass ΣΔ DC utilizing either a single-loop or a MASH architecture where the resonators are implemented as either a delay cell resonator, a delay-cell based resonator or a Forward-Euler resonator is presented.
Abstract: A bandpass ΣΔ DC utilizing either a single-loop or a MASH architecture wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, or a two-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a ΣΔ ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 ΣΔ ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application. The bandpass ΣΔ ADC can also be used in conjunction with undersampling to provide a frequency downconversion.

67 citations


Journal ArticleDOI
TL;DR: In this paper, a switched-capacitor DC-DC converter (SCDDC) can be designed to process up to several tens of watts of output power at an efficiency exceeding 80%.
Abstract: This paper shows that a switched-capacitor DC-DC converter (SCDDC) can be designed to process up to several tens of watts of output power at an efficiency exceeding 80%. Converter operation is analyzed by "modified state-space-averaging", (MSSA) which is generally suitable for analysis of converters with nonlinear ripple. A design procedure is presented along with experimental verification.

Journal ArticleDOI
TL;DR: By performing a detailed analysis of switching-mode power supplies based on swithed-capacitor circuits, their fundamental steady-state characteristics are found.
Abstract: By performing a detailed analysis of switching-mode power supplies based on swithed-capacitor circuits, their fundamental steady-state characteristics are found. A few basic step-down and step-up c...

Patent
Masahiro Tsugai1
19 Aug 1997
TL;DR: In this article, an interface circuit connected to a capacitance type sensor having two sets of capacitors C1 and C2 whose capacitances are varied, equipped with an OP amplifier A1 where a feedback/sampling capacitor C3 is connected between its output terminal and its inverting input terminal; and a holding capacitor C4 connected between a non-inverting terminal of the OP-amplifier A1 and a reference voltage source.
Abstract: In an interface circuit connected to a capacitance type sensor having two sets of capacitors C1 and C2 whose capacitances are varied, this interface circuit is equipped with an OP amplifier A1 where a feedback/sampling capacitor C3 is connected between its output terminal and its inverting input terminal; and a holding capacitor C4 connected between a non-inverting terminal of the OP-amplifier A1 and a reference voltage source; one ends of the respective capacitors C1, C2, C3 are connected to the inverting input terminal of the OP amplifier A1; at timing φ1 of a switching cycle, the other ends of the respective capacitors C1, C2 are connected to a power source and the capacitor C3 is shortcircuited; at timing φ2 thereof, the other ends of the capacitors C1, C2 and an output terminal of the OP amplifier A1 are connected to the non-inverting input terminal of the OP amplifier A1; and the switched capacitor type interface interface circuit further includes: a multiplexer for sequentially connecting a plurality of the capacitance type sensors to the capacitance type sensor interface circuit in a second switching cycle having a time period longer than time periods of the switching cycles φ1 and φ2; and a plurality of sample/hold circuits whose quantity is equal to those of the plural capacitance type sensors, which are sequentially connected to the capacitive type sensor interface circuit in response to the connections of the plural capacitance type sensors in the second switching cycle.

Patent
03 Nov 1997
TL;DR: In this article, a photo-diode is connected in parallel with a switched capacitor to collect charge conducted by the photo, which generates a photo diode voltage, and the switched capacitor can be a gate capacitor.
Abstract: An active pixel sensor. The active pixel sensor includes a photo-diode. The photo-diode conducting charge as a function of the intensity of light received by the photo-diode. The photo-diode includes a diode capacitance which collects charge conducted by the photo-diode which generates a photo-diode voltage. A switched capacitor is connected in parallel with the photo-diode when the photo-diode voltage drops below a pre-determined voltage potential. A capacitance of the switched capacitor adds to the diode capacitance when the switched capacitor is connected. The switched capacitor can be a gate capacitor. The active pixel sensor further includes electronic circuitry to allow a controller to sample the photo-diode voltage.

Journal ArticleDOI
TL;DR: In this paper, a low power, lowvoltage, 12-b 8-kHz bandwidth /spl Sigma/spl Delta/ modulator for high quality voice that consumes only 0.34 mW at 1.95 V-3.3 V supply using standard 1.2-/spl mu/m CMOS technology is described.
Abstract: The design of a low-power, low-voltage, 12-b 8-kHz bandwidth /spl Sigma//spl Delta/ modulator for high-quality voice that consumes only 0.34 mW at 1.95 V supply is described. The modulator employs a special architecture in which a third-order modulator is stabilized by a local feedback loop around each integrator. Unlike multistage /spl Sigma//spl Delta/ modulators, this architecture is very tolerant to the modest dc gain of low voltage op-amps. The architecture, together with special circuit techniques, permits a low-voltage switched capacitor implementation at 1.95 V-3.3 V supply using standard 1.2-/spl mu/m CMOS technology.

Journal ArticleDOI
TL;DR: The pulse waveform applied to the ferroelectric capacitor in the latter approach resembles the actual waveform encountered in a typical ferro electric memory access, making switching-current based models more suitable for use in high-speed-memory circuit simulations.
Abstract: Six different behavioral models for ferroelectric capacitors are surveyed with an emphasis on their usefulness in the transient circuit simulation of integrated nonvolatile memories. These models can be broadly classified into two categories, namely, those that rely on the hysteresis loop and those that rely on the switching current of a ferroelectric capacitor. The former often involves a continuous cycling of a ferroelectric capacitor with a sinusoidal waveform. The latter employs a pulse measurement technique to capture the switching current of the capacitor. The pulse waveform applied to the ferroelectric capacitor in the latter approach resembles the actual waveform encountered in a typical ferroelectric memory access. This resemblance makes switching-current based models more suitable for use in high-speed-memory circuit simulations.

Patent
Samuel H. Nork1
19 Nov 1997
TL;DR: In this paper, a switching regulator circuit using a common switch network on a single IC for providing step-up and step-down DC-DC conversion is provided, which avoids EMI, parasitic and stability concerns particular to inductors and transformers.
Abstract: A switching regulator circuit using a common switch network on a single IC for providing step-up and step-down DC--DC conversion is provided. The switching regulator uses switched capacitor techniques and hence avoids EMI, parasitic and stability concerns particular to inductors and transformers. The converter circuit includes control circuitry for sensing the voltage differential between the input and output to determine whether step-up or step-down mode is to be used. The control circuitry also senses the voltage differential between the input and output and enables the minimum number of switch sections needed to fully regulate the output, using the highest switch resistance possible to minimize inrush current from the input to the output.

Patent
19 Mar 1997
TL;DR: In this paper, the authors use a sequence of non-consecutive code values to determine whether each switch in the converter is functional and use partial settling times during converter testing.
Abstract: Testing of digital-to-analog converters is accelerated by applying one or more different approaches. One approach relies on a switched capacitor, which lowers the overall capacitance of the converter during testing, thereby reducing the settling time for each code value. Another approach makes the duration of each testing step a function of the particular code value, rather than using the worst-case settling time for each testing step. Yet another approach uses a sequence of non-consecutive code values to determine whether each switch in the converter is functional. Using non-consecutive code values permits the use of partial settling times during converter testing. Each of the approaches can be used to accelerate the testing of D/A converters, whether they have linear or folded resistor strings.

Proceedings Article
M. Tuthill1
01 Jan 1997
TL;DR: A Temperature to Digital Converter is described which uses a Sensor based on the principle of switching accurately scaled currents in the parasitic substrate PNP in a standard fine-line CMOS process.
Abstract: A Temperature to Digital Converter is described which uses a Sensor based on the principle of switching accurately scaled currents in the parasitic substrate PNP in a standard fine-line CMOS process. The resulting PTAT δV BE signal is amplified in an Auto-Zeroed Switched-Capacitor circuit, sampled and converted to a Digital output by a low power 10 Bit ADC providing a resolution of 0.25 degree from -55 to 125 degrees with an error of less than 1 degree. The paper will focus on the design of the Sensor.

Journal ArticleDOI
TL;DR: In this article, the authors proposed a switch-capacitor-based step-up DC converter, which can be realized in small size, exhibiting low weight and high power density.
Abstract: A switched-capacitor-based (SC) step-up DC converter is proposed. It contains no inductors and transformers, thus it can be realized in small size, exhibiting low weight and high power density. Two switched-capacitor circuits, operating in antiphase in each half-cycle, are used to control the energy flow from an unregulated voltage source to a regulated output. The capacitors are charged and discharged according to a designed sequence. To enhance the line and load regulation capability, in each half-cycle, each charging interval is split into two subintervals, which are followed by noncharging subintervals whose duration is dictated by the pulsewidth modulation (PWM) feedback circuit. The new converter is advantageous for applications in which significant line drops are likely to occur.

Patent
11 Jun 1997
TL;DR: In this paper, a D/A converter employed in audio systems and various communicating equipment, particularly for using a digital 1-bit data stream as an input and an analog signal as an output, utilizes a charge subtraction method in a low-pass filter instead of employing a bypass filter to prevent an operational amplifier from deviating from a linear range due to a switching noise.
Abstract: In a D/A converter employed in audio systems and various communicating equipment, particularly for using a digital 1-bit data stream as an input and an analog signal as an output, a switched capacitor digital-analog converter having a decreased harmonic distortion utilizes a charge subtraction method in a low-pass filter instead of employing a bypass filter to prevent an operational amplifier from deviating from a linear range due to a switching noise. The bypass capacitor heretofore used in the D/A converter is not employed to shrink the chip designing area.

Patent
07 Jul 1997
TL;DR: In this paper, a column driver for a matrix addressed display such as a liquid crystal display (LCD) is disclosed, which is compatible with digital gamma correction by way of an EPROM lookup table.
Abstract: A column driver for a matrix addressed display such as a liquid crystal display (LCD) is disclosed. The column driver accepts 10-bit inputs, provides 1024 distinct output levels, and is compatible with digital gamma correction by way of, for example, an EPROM lookup table. A complete column driver includes a group of chips which are serially interconnected and receive all the external signals applied in parallel. Only one chip is made active at any instant of time, in order to save power. In each IC, selective polarity inversion of the 10-bit data is carried out before feeding it to a switched capacitor digital to analog converter (CAPDAC) which operates in either a high or low voltage range. All CAPDACs are loaded simultaneously and present a precise output for approximately 95% of each linetime. Each CAPDAC output is connected to a buffer opamp via two CMOS switches which cause the CAPDAC to simultaneously yet transparently change range and allow the opamp buffer to continue driving. The buffer accepts a high impedance, low parasitic input voltage from the CAPDAC array and outputs a low input signal for driving columns with 150-400 pF capacitance. The buffer has an autocalibration circuit that comprises a nested, mini-operational amplifier (opamp) coupled between the output and input of the buffer. The mini-opamp amplifies the balance error produced by the buffer during a calibration interval to provide an output signal which changes the balance point of the buffer amplifier.

Journal ArticleDOI
TL;DR: In this paper, a fully differential comparator was proposed for analog-to-digital converter (ADC) using a switched-capacitor differencing circuit that provides common-mode rejection.
Abstract: A fully differential comparator is described. It uses a switched-capacitor differencing circuit that provides common-mode rejection. The comparator has been tested by building a 3-b flash analog-to-digital converter (ADC) in a 2-/spl mu/m CMOS process. With a supply voltage of 3.3 V, a sampling rate of 25 MHz, and full-scale sinusoidal inputs up to 7 MHz, the signal-to-distortion ratio of the ADC when the input is single ended is about 1-2 dB less than when the input is differential. In a 2-/spl mu/m CMOS process, the comparator occupies 0.25 mm/sup 2/ and dissipates 1.05 mW.

Proceedings ArticleDOI
22 Jun 1997
TL;DR: In this article, a modified topology is proposed for step-down DC/DC switched capacitor power convertors using a multistage structure of switches and capacitors, which can reduce component count by up to one third or more for various designs.
Abstract: Conventional switched capacitor power convertors are unsuitable for many practical applications because of their large component count. A new modified topology is proposed for step-down DC/DC switched capacitor power convertors using a multistage structure of switches and capacitors. The component count can be reduced by up to one third or more for various designs. The ripple output and inrush current also are reduced. Simulation results and their analysis are provided.

Patent
01 Jul 1997
TL;DR: In this paper, the FET's lying on a switching circuit are used to execute a switched capacitor action, where a first capacitor connects to a battery to charge the former at an input power voltage, and after charging, disconnect the first capacitor from the battery but simultaneously connect the first capacitance to a second capacitor to transfer accumulated electric charges to the latter, and a control circuit including a comparator and a voltage controlled oscillator monitors an output voltage from the second capacitor and performs a switching control so that the output voltage is maintained at a specific level.
Abstract: FET's lying on a switching circuit are used to execute a switched capacitor action. The FET's connect a first capacitor to a battery to charge the former at an input power voltage, and after charging, disconnect the first capacitor from the battery but simultaneously connect the first capacitor to a second capacitor to transfer accumulated electric charges to the latter. A control circuit including a comparator and a voltage controlled oscillator monitors an output voltage from the second capacitor and performs a switching control so that the output voltage is maintained at a specific level.

Patent
30 Jun 1997
TL;DR: In this article, an analog-to-digital converter (ADC) and one or more switched capacitor amplifier stages are connected together in series, with the first stage serving as a sample and hold circuit for the ADC.
Abstract: Then circuit includes an analog-to-digital converter (ADC); and one or more switched capacitor amplifier stages connected together in series with a first switched capacitor amplifier stage for receiving the analog input signal, and a last switched capacitor amplifier stage connected to the ADC. Moreover, each of the plurality of switched capacitor amplifier stages preferably has a selectable gain to permit control of an overall gain of the analog input signal upstream of the ADC. In addition, the first stage may also serve as a sample and hold circuit for the ADC. In one embodiment, the circuit may comprise an integrated circuit substrate on which the ADC and the plurality of switched capacitor amplifiers are formed so that the analog-to-digital converter is a monolithic integrated circuit. The circuit may also control the gain of each of the plurality of switched capacitor amplifier stages based upon a digital gain control word. A clock is preferably operatively connected to the ADC and the plurality of switched capacitor amplifier stages. Accordingly, gain control word changes cause relatively rapid changes in the overall gain.

Patent
Wai L. Lee1
11 Mar 1997
TL;DR: In this paper, a switched-capacitor circuit that includes a first signal path disposed between a first input node and a first output node, and a second signal path disposing between a second input node to a second output node is described.
Abstract: A switched-capacitor circuit that includes a first signal path disposed between a first input node and a first output node, and a second signal path disposed between a second input node and a second output node. The first and second switches can be alternately disposed within the first and second signal paths. An amplifier responsive to the switches can be provided, and its offset can be cancelled. The outputs of the amplifiers can be maintained, and this can involve buffering.

Patent
05 Sep 1997
TL;DR: In this article, a second-order double-sampled analog/digital ΣΔ converter using two fully differential switched-capacitors integrators coupled in cascade is presented.
Abstract: A second-order double-sampled analog/digital ΣΔ converter uses two fully differential switched-capacitors integrators coupled in cascade; the first integrator has a fully-floating double-sampled, bilinear switched capacitor input structure, whereas the second integrator has a double-sampled linear switched-capacitor input structure, achieving an excellent SNR with a reduced number of switches for a low consumption.

Patent
21 Feb 1997
TL;DR: In this article, an adaptive bias circuit for switched capacitor applications that compensates for temperature and process variations by maintaining a constant settling time of CMOS operational amplifiers is introduced, which allows a dynamic trade-off between the slew-rate and the gain bandwidth product which allows the output of the operational amplifier to settle within a certain predetermined precision.
Abstract: An adaptive bias circuit for switched capacitor applications that compensates for temperature and process variations by maintaining a constant settling time of CMOS operational amplifiers is introduced. To this end, the adaptive bias circuit allows a dynamic trade-off between the slew-rate and the gain bandwidth product which allows the output of the operational amplifier to settle within a certain predetermined precision. A first aspect of the invention includes a current source providing a same current to a pair of transistors having different effective current densities. A resistor is coupled between the pair of transistors while from one end of the resistor, a constant bias current is drawn. In this manner, a voltage difference develops across the resistor which effectively indicates the change in the transconductance of the pair of transistors with respect to temperature and process variations. Another aspect of the invention allows the bias circuit to minimize the body effect, the back bias effect, the channel length modulation effect, as well as the dependence of circuit performance upon the power supply voltage.

Patent
Hiroshi Yamaguchi1
30 Jul 1997
TL;DR: In this article, an improved charging pump circuit includes first, second, third, fourth and fourth switches connected together in series across an associated power supply, a first capacitor connected between the first and second switches and the ground, and a second capacitance connecting between the third and fourth switch and ground.
Abstract: An improved charging pump circuit includes first, second, third and fourth switches connected together in series across an associated power supply, a first capacitor connected between the first and second switches and the ground, and a second capacitor connected between the third and fourth switches and the ground. One of the first and second switches responds to a first drive signal for turning into a conductive condition while holding the other switch in a non-conductive condition. Likewise, one of the third and fourth switches responds to a second drive signal for turning into the conductive condition while holding the other switch in a non-conductive condition. The time spent for charging or discharging the load capacitor can be substantially reduced by using the first and second capacitors whose capacitances are much smaller than the capacitance of a load capacitor, and accordingly jitter can be reduced in a PPL circuit in which the charging pump circuit is included.