Showing papers on "Switched capacitor published in 2005"

Design-oriented estimation of thermal noise in switched-capacitor circuits

Abstract: Thermal noise represents a major limitation on the performance of most electronic circuits. It is particularly important in switched circuits, such as the switched-capacitor (SC) filters widely used in mixed-mode CMOS integrated circuits. In these circuits, switching introduces a boost in the power spectral density of the thermal noise due to aliasing. Unfortunately, even though the theory of noise in SC circuits is discussed in the literature, it is very intricate. The numerical calculation of noise in switched circuits is very tedious, and requires highly sophisticated and not widely available software. The purpose of this paper is twofold. It provides a tutorial description of the physical phenomena taking place in an SC circuit while it processes noise (Sections II-III). It also proposes some specialized but highly efficient algorithms for estimating the resulting sampled noise in SC circuits, which need only simple calculations (Sections IV-VI ). A practical design procedure, which follows directly from the estimate, is also described. The accuracy of the proposed estimation algorithms is verified by simulation using SpectreRF. As an example, it is applied to the estimation of the total thermal noise in a second-order low-distortion delta-sigma converter.

Design and analysis of switched-capacitor-based step-up resonant converters

Abstract: A switched-capacitor-based step-up resonant converter is proposed. The voltage conversion of the converters is in step-up mode. By adding a different number of switched-capacitor cells, different output voltage conversion ratios can be obtained. The voltage conversion ratio from 2 to any whole number can therefore be generated by these switching-capacitor techniques. A resonant tank is used to assist in zero-current switching hence the current spike, which usually exists for classical switched-capacitor can be eliminated. Both high-frequency operations and high efficiency are possible. Generalized analysis and design method of the converters are also presented. Experimental results verified the theoretical analysis.

High-level synthesis of switched-capacitor, switched-current and continuous-time /spl Sigma//spl Delta/ modulators using SIMULINK-based time-domain behavioral models

Abstract: This paper presents a high-level synthesis tool for /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for /spl Sigma//spl Delta/M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of /spl Sigma//spl Delta/Ms using both discrete-time and continuous-time circuit techniques.

A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion

Abstract: A cascade of sigma-delta modulator stages that employ a feedforward architecture to reduce the signal ranges required at the integrator inputs and outputs has been used to implement a broadband, high-resolution oversampling CMOS analog-to-digital converter capable of operating from low-supply voltages. An experimental prototype of the proposed architecture has been integrated in a 0.25-/spl mu/m CMOS technology and operates from an analog supply of only 1.2 V. At a sampling rate of 40 MSamples/sec, it achieves a dynamic range of 96 dB for a 1.25-MHz signal bandwidth. The analog power dissipation is 44 mW.

Zero-current-switching switched-capacitor bidirectional DC-DC converter

Abstract: The proposed zero-current-switching switched-capacitor quasi-resonant DC-DC converter is a new type of bidirectional power flow control conversion scheme. It possesses the conventional features of resonant switched-capacitor converters: low weight, small volume, high efficiency, low EMI emission and current stress. A zero-current-switching switched-capacitor step-up/step-down bidirectional converter is presented that can improve the current stress problem during bidirectional power flow control processing. It can provide a high voltage conversion ratio using four power MOSFET main switches, a set of switched capacitors and a small resonant inductor. The converter operating principle of the proposed bidirectional power conversion scheme is described in detail with circuit model analysis. Simulation and experiment are carried out to verify the concept and performance of the proposed bidirectional DC-DC converter.

Modeling of capacitor impedance in switching converters

Abstract: Switched capacitor (SC) converters are gaining acceptance as alternatives to traditional, inductor-based switching power converters. Proper design of SC converters requires an understanding of all loss sources and their impacts on circuit operation. In the present work, an equivalent resistance method is developed for analysis, and equivalent resistance formulae are presented for various modes of operation. Quasiresonant converters are explored and compared to standard SC converters. Comparisons to inductor-based switching power converters are made. A number of capacitor technologies are evaluated and compared for applications to both SC converters and inductor-based converters. The resulting model can be used to accurately predict and optimize converter performance in the design phase.

A cascade boost-switched-capacitor-converter - two level inverter with an optimized multilevel output waveform

Abstract: Two structures, a switched-capacitor (SC)-based boost converter and a two-level inverter, are connected in cascade. The dc multilevel voltage of the first stage becomes the input voltage of the classical inverter, resulting in a staircase waveform for the inverter output voltage. Such a multilevel waveform is close to a sinusoid; its harmonics content can be reduced by multiplying the stage number of the SC converter. The output low-pass filter, customary after a two-level inverter, becomes obsolete, resulting in a small size of the system, as the SC circuit can be miniaturized. Both stages are operated at a high switching frequency, resulting in a high-frequency inverter output, as required by some industrial applications. A Fourier analysis of the output waveform is performed. The design is optimized with reference to the nominal duty-cycle for obtaining the minimum total harmonic distortion. Simulations and experiments on two prototypes, one with a five-level output and one with a seven-level output, confirm the theoretical analysis.

An adaptive impedance tuning CMOS circuit for ISM 2.4-GHz band

Abstract: The difficulties encountered in matching an antenna to its optimal impedance are reduced with an adaptive 0.35-/spl mu/m CMOS circuit based on several switched shunt capacitors arranged in capacitor banks and on a few external series inductors. As high-quality inductors are difficult to obtain in CMOS, the inductors are placed either in an low-temperature cofired ceramic (LTCC) substrate or is a lumped component outside the core circuit. The circuits, presented here through a range of simulations, are optimized to function within the ISM 2.4-GHz band, but the general approach employed to improve matching can be used for other frequency bands as well. The circuits discussed provide a VSWR/spl les/2 match for every impedance with VSWR/spl les/5. There is a 1-dB power loss for a perfect 50 /spl Omega//spl rarr/50 /spl Omega/ transformation, a break-even point at VSWR=1.5, and a 3-dB increase in delivered power for VSWR= 4.3.

Hybrid switched-capacitor-Cuk/Zeta/Sepic converters in step-up mode

Abstract: The energy-transfer-capacitor in basic Cuk, Zeta and Sepic converters is split into two capacitors. The rectifier diode is replaced by two diodes that form with the two capacitors a switched-capacitor circuit, which appears connected between the input and output inductances of the original converter. As a result, hybrid circuits, presenting a higher DC voltage ratio than the classical Cuk, Zeta and Sepic converters, are obtained. Even if the new hybrid structures do not reach the DC gain of quadratic converters, they present a higher efficiency in processing the energy: unlike the cascaded converters whose efficiency is a product of the efficiencies of each block, the hybrid converters do not require an additional level of energy processing. A DC analysis, simulation and experimental results concerning the proposed circuits are presented.

Analysis and design of switched capacitor converters

Abstract: Switched capacitor converters have become more common in recent years. Crucial to understanding the maximum power throughput and efficiency is a model of the converter's equivalent resistance. A new form for equivalent resistance is derived and discussed in a design context. Quasi-resonant operation is also explored and compared to non-resonant operation. Several capacitor technologies are evaluated and compared

The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application

Abstract: The impact of CMOS technology scaling on the various radio frequency (RF) circuit components such as active, passive and digital circuits is presented Firstly, the impact of technology scaling on the noise and linearity of the low-noise amplifier (LNA) is thoroughly analyzed Then two new circuits, ie, CMOS complementary parallel push-pull (CCPP) circuit and vertical-NPN (V-NPN) circuit for direct-conversion receiver (DCR), are introduced In CCPP, the high RF performance of pMOS comparable to nMOS provides single ended differential RF signal processing capability without the use of a bulky balun The use of parasitic V-NPN bipolar transistor, available in triple well CMOS technology, has shown to provide more than an order of magnitude improvement in 1/f noise and dc offset related problems, which have been the bottleneck for CMOS single chip integration Then CMOS technology scaling for various passive device performances such as the inductor, varactor, MIM capacitor, and switched capacitor, is discussed Both the forward scaling of the active devices and the inverse scaling of interconnection layer, ie, more interconnection layers with effectively thicker total dielectric and metal layers, provide very favorable scenario for all passive devices Finally, the impact of CMOS scaling on the various digital circuits is introduced, taking the digital modem blocks, the various digital calibration circuits, the switching RF power amplifier, and eventually the software defined radio, as examples

Modeling of switched-capacitor delta-sigma Modulators in SIMULINK

Abstract: Precise behavioral modeling of switched-capacitor /spl Delta//spl Sigma/ modulators is presented. Considering noise (switches' and op-amps' thermal noise), clock jitter, nonidealities of integrators and op-amps including finite dc-gain (DCG) and unity gain bandwidth, slew-limiting, DCG nonlinearities and the input parasitic capacitance, quantizer hysteresis, switches' clock-feedthrough, and charge injection, exhaustive behavioral simulations that are close models of the transistor-level ones can be performed. The DCG nonlinearity of the integrators, which is not considered in many /spl Delta//spl Sigma/ modulators' modeling attempts, is analyzed, estimated, and modeled. It is shown that neglecting this parameter would lead to a significant underestimation of the modulators' behavior and increase the noise floor as well as the harmonic distortion at the output of the modulator. Evaluation and validation of the models were done via behavioral and transistor-level simulations for a second-order modulator using SIMULINK and HSPICE with a generic 0.35-/spl mu/m CMOS technology. The effects of the nonidealities and nonlinearities are clearly seen when compared to the ideal modulator in the behavioral and actual modulator in the circuit-level environment.

A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC

Abstract: A pipelined analog-to-digital converter (ADC) architecture suitable for high-speed (150 MHz), Nyquist-rate A/D conversion is presented. At the input of the converter, two parallel track-and-hold circuits are used to separately drive the sub-ADC of a 2.8-b first pipeline stage and the input to two time-interleaved residue generation paths. Beyond the first pipeline stage, each residue path includes a cascade of two 1.5-b pipeline stages followed by a 4-b "backend" folding ADC. The full-scale residue range at the output of the pipeline stages is half that of the converter input range in order to conserve power in the operational amplifiers used in each residue path. An experimental prototype of the proposed ADC has been integrated in a 0.18-/spl mu/m CMOS technology and operates from a 1.8-V supply. At a sampling rate of 150 MSample/s, it achieves a peak SNDR of 45.4 dB for an input frequency of 80 MHz. The power dissipation is 71 mW.

Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler

Abstract: Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doublers based on cross-coupled structure are presented. The intuitive analysis of the shoot-through current and switching noise generation processes in the doubler is first reported. Break-before-make mechanism is adopted to minimize the shoot-through current, thereby greatly reducing the no-load supply current dissipation and improving the light-load power efficiency of the voltage doubler. In addition, by employing gate-slope reduction technique at the serial power transistor during turn-on, the switching noise of the voltage doubler is significantly lowered. Two voltage doublers with and without the proposed circuit techniques have been fabricated in a 0.6-/spl mu/m CMOS process. Experimental results verify that the total supply current at no-load condition of the proposed voltage doubler is reduced by two fold and its switching noise is decreased by 2.5 times.

Capacitive sensor interfacing using sigma-delta techniques

Abstract: A monolithic precision capacitive sensor interface based on a Sigma-Delta core is presented. All necessary functions such as sensor excitation, temperature sensor, voltage reference, etc. are included. Traditionally the most widely used method for digitizing the output of a capacitive sensor was to first convert the capacitance to a voltage, followed by a regular ADC. The presented interface circuit directly converts a capacitance to a digital word, at high resolution (2aF/sqrtHz), high linearity (100ppm) and high accuracy (4fF). The circuit is based on a novel modification to a standard switched-cap Sigma-Delta modulator. The fixed input capacitor in the switched capacitor front-end is replaced by the external variable sensor capacitance, and a fixed voltage is applied in place of the normal variable voltage input. A fully differential circuit is used in conjunction with a switching technique which allows for cancellation of leakage current errors. The circuit is also insensitive to parasitic capacitance to ground

A cost-efficient high-speed 12-bit pipeline ADC in 0.18-/spl mu/m digital CMOS

Abstract: A 12-bit pipeline ADC fabricated in a 0.18-/spl mu/m pure digital CMOS technology is presented. Its nominal conversion rate is 110 MS/s and the nominal supply voltage is 1.8 V. The effective number of bits is 10.4 when a 10-MHz input signal with 2V/sub P-P/ signal swing is applied. The occupied silicon area is 0.86 mm/sup 2/ and the power consumption equals 97 mW. A switched capacitor bias current generator scales the opamp bias currents automatically with the conversion rate, which gives scaleable power consumption and full performance of the ADC from 20 to 140 MS/s.

Variable capacitance switched capacitor input system and method

Abstract: A variable capacitance switched capacitor input system and method includes a differential integrator circuit having first and second input summing nodes and a variable sensing capacitor; one terminal of the variable sensing capacitor is connected to one of the nodes in the first phase and to the other of the nodes in the second phase; an input terminal connected to a second terminal of the variable sensing capacitor receives a first voltage level in the first phase and a second voltage level in the second phase for delivering the charge on the variable sensing capacitor to the first summing node in the first phase and to the second summing node in the second phase and canceling errors in a differential integrator circuit output caused by leakage current.

Noise-shaping techniques applied to switched-capacitor voltage regulators

Abstract: A delta-sigma control loop for a buck-boost dc-dc converter with fractional gains is presented. This technique reduces the tones caused by the traditional pulse-frequency modulation regulation. The prototype regulator was fabricated in a 0.72-/spl mu/m CMOS process and clocked at 1 MHz. It achieved suppression of tones up to 55 dB in the 0-500-kHz range. The input voltage range was 3-5 V. The output voltage ranged from 1.8 to 4 V for load currents up to 150 mA.

An On-Chip Spectrum Analyzer for Analog Built-In Testing

Abstract: This paper presents an analog built-in testing (BIT) architecture and its implementation. It enables the frequency response and harmonic distortion characterizations of an integrated device-under-test (DUT) through a digital off-chip interface. External analog instrumentation is avoided, reducing test time and cost. The proposed on-chip testing scheme uses a digital frequency synthesizer and a simple signal generator synchronized with a switched capacitor bandpass filter. A general methodology for the use of this structure in the functional verification of a DUT is also provided. The circuit-level design and experimental results of an integrated prototype in standard CMOS 0.5 ?m technology are presented to demonstrate the feasibility of the proposed BIT technique.

Charge-pump-type power supply circuit

Abstract: Two charge pump circuits are connected in a cascade manner. Each of the charge pump circuits includes two charging switches and two voltage-boosting switches. A voltage-boosting switch, provided on a side for adding a boosting voltage to a charging voltage in a second-stage charge pump circuit, includes a plurality of switches. One ends of the switches are commonly connected to a capacitor. Different boosting voltages are applied to other ends of the switches. A selecting unit selects one of the switches, during a boosting period, based on an input voltage or an output voltage to or from a first-stage charge pump circuit.

Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization

Abstract: This paper presents the design and characterization of a sample-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch. The heart of this circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced, resulting in improved sample-and-hold accuracy. Experimental results in a 0.18 /spl mu/m digital CMOS process show that a resolution greater than 10 bits can be obtained with a 1.0 V supply voltage. Circuit operation is also possible for supply voltages close to the transistor threshold (e.g., 0.65 V).

Highly-selective electronically-tunable cryogenic filters using monolithic, discretely-switchable MEMS capacitor arrays

Abstract: A low loss electronically tunable filter was demonstrated using HTS/Au MEMS switched capacitor arrays. The two-pole filter was tuned by simultaneously varying the capacitance of each resonator by equal amounts. A K factor of between 3,500 and 5,000 was demonstrated for single pole resonators. The total tuning range was about 25% with an average Q of 7,000 at 77 K.

A cost-efficient high-speed 12-bit pipeline ADC in 0.18-μm digital CMOS

Abstract: A 12-bit pipeline ADC fabricated in a 0.18-μm pure digital CMOS technology is presented. Its nominal conversion rate is 110 MS/s and the nominal supply voltage is 1.8 V. The effective number of bits is 10.4 when a 10-MHz input signal with 2Vp―p signal swing is applied. The occupied silicon area is 0.86 mm 2 and the power consumption equals 97 mW. A switched capacitor bias current generator scales the opamp bias currents automatically with the conversion rate, which gives scaleable power consumption and full performance of the ADC from 20 to 140 MS/s.

Switched-capacitor circuit with scaled reference voltage

Abstract: A pipelined analog-to-digital converter (ADC) (30) with improved precision is disclosed. The pipelined ADC (30) includes a sequence of stages (20), each of which includes a sample-and-hold circuit (22), an analog-to-digital converter (23), and the functions of a digital-to-analog converter (DAC) (25), an adder (24), and a gain stage (27) at which a residue signal (RES) is generated for application to the next stage (20) in the sequence. A multiplying DAC performs the functions of the DAC (25), adder (24), and gain stage (27) in the stage (20), and is based on an operational amplifier. Sample capacitors and reference capacitors receive the analog input from the sample-and-hold circuit (22) in a sample phase; parallel capacitors are provided to maintain constant circuit gain. Extended reference voltages (VREFNX VREFNX) at levels that exceed the output range of the operational amplifier are applied to the reference capacitors, in response to the digital output of the analog-to-digital converter (23) in its stage (20). The reference capacitors are scaled according to the extent to which the extended reference voltages (VREFNX VREFNX) exceed the op amp output levels. The effects of noise on the reference voltages (VREFNX VREFNX) on the residue signal (RES) are thus greatly reduced.

Continuous-time common-mode feedback for high-speed switched-capacitor networks

Abstract: This paper deals with the design of a continuous-time common-mode feedback (CMFB) for switched-capacitor networks. Its reduced input capacitance decreases the capacitive load at the output of the fully differential amplifier, improving its achievable gain-bandwidth (GBW) product and slew rate. This topology is more suitable for high-speed switched-capacitor applications when compared to a conventional switched-capacitor CMFB, enabling operation at higher clock frequencies. Additionally, it provides a superior rejection to the negative power supply noise (PSRR/sup -/). The performance of the CMFB is demonstrated in the implementation of a second-order 10.7-MHz bandpass switched-capacitor filter and compared with that of an identical filter using the conventional switched-capacitor CMFB (SC-CMFB). The filter using the continuous-time CMFB reduces the error due to finite GBW and slew rate to less than 1% for clock frequencies up to 72 MHz while providing a dynamic range of 59 dB and a PSRR/sup -/>22 dB. Both circuits were fabricated in 0.35-/spl mu/m CMOS technology.

Amplifying solid-state image pickup device

Abstract: There is provided an amplifying solid-state image pickup device capable of improving S/N and maintaining a charge-voltage conversion efficiency high. In the amplifying solid-state image pickup device, signal charges of a plurality of photodiodes 1 are added up on an input side of a switched capacitor amplification part 20 via the transfer transistors 2.

A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta Modulator for low-power high-linearity automotive sensor ASICs

Abstract: This paper describes a 0.35-/spl mu/m CMOS chopper-stabilized switched-capacitor 2-1 cascade /spl Sigma//spl Delta/ modulator for automotive sensor interfaces. The modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed and power dissipation. To obtain a better fitting with the characteristics of different sensor outputs, the circuit can be digitally programmed to yield four input-to-output gain values (/spl times/0.5,/spl times/1,/spl times/2, and /spl times/4) and has been designed to operate within the stringent environmental conditions of automotive electronics (temperature range of -40/spl deg/C to 175/spl deg/C). In order to relax the amplifier's dynamic requirements for the different modulator input-to-output gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12 MHz and the overall power consumption is 14.7 mW from a single 3.3-V supply and occupies 5.7 mm/sup 2/ silicon area. Experimental results show a maximum SNR of 87.3 dB within a 20-kHz signal bandwidth and 90.7 dB for 10-kHz signals, and an overall DR of 110 and 113.8dB, respectively. These performance features place the reported circuit at the cutting edge of state-of-the-art high-resolution /spl Sigma//spl Delta/ modulators.

On the optimization of ultra low power front-end interfaces for capacitive sensors

Abstract: Traditionally, most of the sensor interfaces must be tailored towards a specific application. This design approach is inflexible and requires several iteration steps for new sensor applications. It usually results in high costs for low and medium quantity market products. On the other hand, generic interface design reduces the costs and may provide a handy solution for multisensor applications. This paper presents a new generic architecture for ultra low power (ULP) capacitive sensor systems. It consists of a sensor interface followed by a modulator. The sensor interface (capacitance to voltage converters and switched capacitor (SC) amplifier) works on a lower clock frequency, 8 kHz, than the modulator, 128 kHz, to achieve very low power consumption. A new capacitance to voltage converter with class AB and correlated double sampling (CDS) operation reduces the shunt conductance leakage. The system maintains a smart power management by adapting biasing currents, measurement time and duty cycle according to the needs of the application (parasitic element reduction, accuracy and speed). The proposed architecture provides an interface to a broad range of capacitive sensors. The simulations show that the readout circuitry consumes merely 29 μA in operational mode with a 3 V power supply.

Full order dynamic model of SEPIC converter

Abstract: In this paper a full order dynamic model of the non-isolated and isolated DC-DC SEPIC (single ended primary inductance converter) is presented The switches (transistor and diode) are substituted by PWM averaged switch model equivalent circuit The SEPIC converter is used in the cases when the wide range of input voltages has been required There are two inductors and two capacitors inside the converter circuit Due to this, its mathematical model is of the fourth order differential equations system Duty-cycle and transformer turn ratio have impact on the converter dynamics The derived dynamic model was verified by simulation toolbox Sim PowerSystems

A high-precision wide-range front-end for resistive gas sensors arrays

Abstract: In this paper, a high-precision wide-range electronic front-end for resistive gas sensors is described. A flexible continuous time trans-resistance stage is followed by a switched capacitor incremental ADC. A smart DSP allows to reconfigure the front-end in order to achieve a resolution of 0.1% for a resistance ranging in [100 Ω–10 MΩ].